Publications associées à Fonction NON

Nicolas Grandjean, Jean-François Carlin

Hot-electron temperature (T-e) in InAlN/GaN high-electron-mobility transistors (HEMTs) was determined using electroluminescence spectroscopy as a function of gate voltage and correlated with the Te distribution determined by hydrodynamic simulations. Good ...

Ieee-Inst Electrical Electronics Engineers Inc2014

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS tra ...

2014

Ultra low power NEMFET based logic

Mihai Adrian Ionescu, Antonios Bazigos, Surya Shankar Dan

In this paper, we introduce a Nano-Electro-Mechanical Field Effect Transistor (NEMFET) based logic family tailored to the implementation of low speed and ultra low energy functional units and processors. Basic Boolean gates implemented with NEMFETs only ar ...

IEEE2013

Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Ogün Türkyilmaz

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to perma ...

2013

FinFET integrated low-power circuits for enhanced sensing applications

Mihai Adrian Ionescu, Antonios Bazigos, Alexandru Rusu, Sara Rigante, Paolo Livi

This work presents different circuit architectures that combine sensing and signal readout functions. The basic building block is a Fin Field-Effect Transistor (Fin-FET) used as both sensor and metal gate transistor. Moreover, a hybrid partially gated FinF ...

Elsevier2013

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba, Michele De Marchi

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Jian Zhang

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar trans ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

Mihai Adrian Ionescu, Didier Bouvet, Luca De Michielis, Cem Alper, Livio Lattanzio, Nilay Dagtekin

We report the significant improvement obtained by a non-uniform gate capacitance made by appropriate combination of high-k and low-k regions over the tunneling and the channel regions of a heterostucture TFET (called HKLKFFET). In addition to significantly ...

Elsevier2013

Single electron transistors with ultra-thin Au nanowires as a single Coulomb island

Hoël Maxime Guérin

Single electron transistors exhibiting transport properties based on a single Coulomb island have been fabricated using ultra-thin gold nanowires (AuNWs), which are synthesized via a chemical reduction process. The AuNWs are bottom-contacted with source an ...

American Institute of Physics2013

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Fonction NON

Hot-Electron-Related Degradation in InAlN/GaN High-Electron-Mobility Transistors

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Ultra low power NEMFET based logic

Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET

FinFET integrated low-power circuits for enhanced sensing applications

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

Single-layer MoS₂

Single electron transistors with ultra-thin Au nanowires as a single Coulomb island

Graph Chatbot

Chattez avec Graph Search

Hot-Electron-Related Degradation in InAlN/GaN High-Electron-Mobility Transistors

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Ultra low power NEMFET based logic

Single electron transistors with ultra-thin Au nanowires as a single Coulomb island

Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET

FinFET integrated low-power circuits for enhanced sensing applications

Single-layer MoS₂

Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors