Publications associées à Placement-routage

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

Paolo Ienne, Grace Zgheib, Philip Brisk, Hadi Parandeh Afshar

Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2011

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Giovanni De Micheli, Shashi Kanth Bobba, Thomas Ernst

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contac ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Towards generic low-power area-efficient standard cell based memory architectures

Andreas Peter Burg, Pascal Andreas Meinerzhagen

Digital IC designers often use SRAM macrocells to implement on-chip memory functionality. In this paper we argue that in several situations, standard cell based memories (SCMs) can have advantages over SRAM macrocells. Various ways to implement SCMs are pr ...

IEEE2010

Synthesis of regular computational fabrics with ambipolar CNTFET technology

Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Shashi Kanth Bobba, Michele De Marchi

In this paper, we report on a physical design of regular fabrics with ambipolar CNTFET devices. Three mediumgrain size cells, built with ambipolar CNTFETs with in-field controllable polarities are evaluated. We designed regular layouts using these cells us ...

2010

Exploiting Fast Carry-Chains Of Fpgas For Designing Compressor Trees

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry c ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Synthesis of Networks on Chips for 3D Systems on Chips

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...

2009

An Experimental Platform for an Indoor Location and Tracking System

Pierre-André Farine, Cyril Botteron, Frédéric Chastellain

In this paper, an experimental platform for indoor location and tracking using ultra wideband (UWB) impulse radio signals is presented and its performance measured. The platform has been developed entirely using standard electronic components that are comm ...

2008

CONFETTI : A reconfigurable hardware platform for prototyping cellular architectures

Daniel Mange, Pierre-André Mudry, Fabien Vannel

In this article, we describe a novel hardware platform aimed at the realization of cellular architectures. The system is built hierarchically from a very simple computing unit, called ECell. Several of these units can then be connected, using a high-speed ...

2007

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Placement-routage

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Towards generic low-power area-efficient standard cell based memory architectures

Synthesis of regular computational fabrics with ambipolar CNTFET technology

Exploiting Fast Carry-Chains Of Fpgas For Designing Compressor Trees

Synthesis of Networks on Chips for 3D Systems on Chips

An Experimental Platform for an Indoor Location and Tracking System

CONFETTI : A reconfigurable hardware platform for prototyping cellular architectures

A system for automatic on-line time detection and classification of neural spikes based on a digital signal processor and a FPGA controller

Thermal Characterization and Thermal Management in Processor-Based Systems

Graph Chatbot

Chattez avec Graph Search

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Synthesis of Networks on Chips for 3D Systems on Chips

Towards generic low-power area-efficient standard cell based memory architectures

Exploiting Fast Carry-Chains Of Fpgas For Designing Compressor Trees

Thermal Characterization and Thermal Management in Processor-Based Systems

CONFETTI : A reconfigurable hardware platform for prototyping cellular architectures

Synthesis of regular computational fabrics with ambipolar CNTFET technology

An Experimental Platform for an Indoor Location and Tracking System

A system for automatic on-line time detection and classification of neural spikes based on a digital signal processor and a FPGA controller