Publications associées à Page (computer memory)

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

Anastasia Ailamaki, Periklis Chrysogelos, Angelos Christos Anadiotis, Syed Mohammad Aunn Raza

Most modern in-memory online transaction processing (OLTP) engines rely on multi-version concurrency control (MVCC) to provide data consistency guarantees in the presence of conflicting data accesses. MVCC improves concurrency by generating a new version o ...

ACM2023

A Large-Scale Characterization of How Readers Browse Wikipedia

Robert West, Tiziano Piccardi, Akhil Arora

Despite the importance and pervasiveness of Wikipedia as one of the largest platforms for open knowledge, surprisingly little is known about how people navigate its content when seeking information. To bridge this gap, we present the first systematic large ...

ASSOC COMPUTING MACHINERY2023

Rethinking Software Runtimes for Disaggregated Memory

Sanidhya Kashyap, Ivan Puddu

Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual mem ...

ASSOC COMPUTING MACHINERY2021

Access pattern based optimization of memory access

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include identifying an access pattern associated with a database operation. The access pattern may include data required to perform the database operation. One or mor ...

2020

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

Perovskite Flash Memory with a Single-Layer Nanofloating Gate

Mohammad Khaja Nazeeruddin, Peng Gao, Hobeom Kim

Here we use triple-cation metal-organic halide perovskite single crystals for the transistor channel of a flash memory device. Moreover, we design and demonstrate a 10 nm thick single-layer nanofloating gate. It consists of a ternary blend of two organic s ...

2020

Prefetched Address Translation

Edouard Bugnion, Boris Robert Grot, Dmitrii Ustiugov

With explosive growth in dataset sizes and increasing machine memory capacities, per-application memory footprints are commonly reaching into hundreds of GBs. Such huge datasets pressure the TLB, resulting in frequent misses that must be resolved through a ...

ASSOC COMPUTING MACHINERY2019

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Page (computer memory)

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

Rebooting Virtual Memory with Midgard

A Large-Scale Characterization of How Readers Browse Wikipedia

Rethinking Software Runtimes for Disaggregated Memory

Access pattern based optimization of memory access

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Gain-Cell Embedded DRAMs: Modeling and Design Space

Perovskite Flash Memory with a Single-Layer Nanofloating Gate

Prefetched Address Translation

Timely and cost-efficient data exploration through adaptive tuning

Graph Chatbot

Chattez avec Graph Search

Rebooting Virtual Memory with Midgard

Perovskite Flash Memory with a Single-Layer Nanofloating Gate

A Large-Scale Characterization of How Readers Browse Wikipedia

Access pattern based optimization of memory access

Prefetched Address Translation

Timely and cost-efficient data exploration through adaptive tuning

Gain-Cell Embedded DRAMs: Modeling and Design Space

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

Rethinking Software Runtimes for Disaggregated Memory