Publications associées à Espresso heuristic logic minimizer

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Giovanni De Micheli, Alessandro Tempia Calvino

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

2024

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

New York2023

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Giovanni De Micheli, Andrea Costamagna

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

IEEE2022

Decentralized Proximal Gradient Algorithms With Linear Convergence Rates

Ali H. Sayed, Kun Yuan, Sulaiman A S A E Alghunaim

This article studies a class of nonsmooth decentralized multiagent optimization problems where the agents aim at minimizing a sum of local strongly-convex smooth components plus a common nonsmooth term. We propose a general primal-dual algorithmic framewor ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism

Giovanni De Micheli, Mathias Soeken, Winston Jason Haaswijk

Exact synthesis is a versatile logic synthesis technique with applications to logic optimization, technology mapping, synthesis for emerging technologies, and cryptography. In recent years, advances in SAT solving have lead to a heightened research effort ...

2020

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Circuits naturally exhibit recurring patterns of local interconnect. Hardening those patterns when designing Field Programmable Gate Array (FPGA) clusters can both eliminate slow programmable connections from the critical path and remove the need for trans ...

IEEE2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa

Reducing the number of AND gates plays a central role in many cryptography and security applications. We propose a logic synthesis algorithm and tool to minimize the number of AND gates in a logic network composed of AND, XOR, and inverter gates. Our appro ...

ASSOC COMPUTING MACHINERY2019

Scaling-up ESOP Synthesis for Quantum Compilation

Giovanni De Micheli, Mathias Soeken, Bruno Schmitt Antunes

Today's rapid advances in quantum computing hardware call for scalable synthesis methods to map combinational logic represented as multi-level Boolean networks (e.g., an and inverter graph, AIG) to quantum circuits. Such synthesis process must yield revers ...

IEEE2019

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Espresso heuristic logic minimizer

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Improving Standard-Cell Design Flow using Factored Form Optimization

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

A chance-constraint approach for optimizing Social Engagement-based services

Decentralized Proximal Gradient Algorithms With Linear Convergence Rates

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications

Scaling-up ESOP Synthesis for Quantum Compilation

Graph Chatbot

Chattez avec Graph Search

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Scaling-up ESOP Synthesis for Quantum Compilation

Improving Standard-Cell Design Flow using Factored Form Optimization

A chance-constraint approach for optimizing Social Engagement-based services

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Decentralized Proximal Gradient Algorithms With Linear Convergence Rates

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications