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Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...
2024
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The paper presents a generalization of DAG-aware AIG rewriting for k-feasible Boolean networks, whose nodes are k-input lookup tables (k-LUTs). We introduce a high-effort DAG-aware rewriting algorithm, called cut rewriting, which uses exact synthesis to co ...
IEEE2019
This thesis introduces “constraint-based graphic statics”, a geometrical support for computer-aided structural design. This support increases the freedom with which the designer interacts with the plane static equilibriums being shaped. Constraint-based gr ...
The beginning of 21st century provided us with many answers about how to reach the channel capacity. Polarization and spatial coupling are two techniques for achieving the capacity of binary memoryless symmetric channels under low-complexity decoding algor ...
This paper presents an algorithm for the fully dynamic biconnectivity problem whose running time is exponentially faster than all previously known solutions. It is the first dynamic algorithm that answers biconnectivity queries in time O(pow2(log(n)) in a ...
Linear Threshold Boolean units (LTU) are the basic processing components of artificial neural networks of Boolean activations. Quantization of their parameters is a central question in hardware implementation, when numerical technologies are used to store ...
Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...
This thesis presents NC(T), an extension of the DPLL(T) scheme [16, 29] for decision procedures for quantifier-free first-order logics. In DPLL(T), a general Boolean DPLL engine is instantiated with a theory solver for the theory T. The DPLL engine is resp ...
A Majority-Inverter Graph (MIG) is a homogeneous logic network, where each node represents the majority function. Recently, a logic optimization package based on the MIG data-structure, with 3-input majority node (M3) has been proposed [2], [30]. It is dem ...
This paper introduces computational techniques to support architects and structural designers in the shaping of strut-and-tie networks in static equilibrium. Taking full advantage of geometry, these techniques build on the reciprocal diagrams of graphic st ...
