Publications associées à Pipeline (computing)

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch

The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is oe ...

2017

Single-FPGA complete 3D and 2D medical ultrasound imager

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim, Damien Doy

3D ultrasound (US) acquisition acquires volumetric images, thus alleviating a classical US imaging bottleneck that requires a highly-trained sonographer to operate the US probe. However, this opportunity has not been explored in practice, since 3D US machi ...

IEEE2017

Machine Vision Algorithms on Cadaster Plans

Isabella Di Lenardo, Sofia Ares Oliveira

Cadaster plans are cornerstones for reconstructing dense representations of the history of the city. They provide information about the city urban shape, enabling to reconstruct footprints of most important urban components as well as information about the ...

2017

Machine Vision Algorithms on Cadaster Plans

Frédéric Kaplan, Isabella Di Lenardo, Sofia Ares Oliveira

2017

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

Executing a dataflow program on a parallel platform requires assigning to each buffer a given size so that correct program executions take place without introducing any deadlock. Furthermore, in the case of dynamic dataflow programs, specific buffer size a ...

2017

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Marco Mattavelli, Endri Bezati, Ab Al Hadi Bin Ab Rahman, Anatoly Prihozhy

This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are th ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

Hierarchical Cycle Accounting: A New Method for Application Performance Tuning

Willy Zwaenepoel, Andrzej Pawel Nowak

To address the growing difficulty of performance debugging on modern processors with increasingly complex micro-architectures, we present Hierarchical Cycle Accounting (HCA), a structured, hierarchical, architecture-agnostic methodology for the identificat ...

2015

FIR filters for hardware-based real-time multi-band image blending

Yusuf Leblebici, Vladan Popovic

Creating panoramic images has become a popular feature in modern smart phones, tablets, and digital cameras. A user can create a 360 degree field-of-view photograph from only several images. Quality of the resulting image is related to the number of source ...

Spie-Int Soc Optical Engineering2015

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Pipeline (computing)

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

Single-FPGA complete 3D and 2D medical ultrasound imager

Machine Vision Algorithms on Cadaster Plans

Machine Vision Algorithms on Cadaster Plans

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Machine Vision algorithms on cadaster plans

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Hierarchical Cycle Accounting: A New Method for Application Performance Tuning

FIR filters for hardware-based real-time multi-band image blending

Graph Chatbot

Chattez avec Graph Search

Machine Vision Algorithms on Cadaster Plans

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Machine Vision Algorithms on Cadaster Plans

Machine Vision algorithms on cadaster plans

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Hierarchical Cycle Accounting: A New Method for Application Performance Tuning

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

FIR filters for hardware-based real-time multi-band image blending

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

Single-FPGA complete 3D and 2D medical ultrasound imager