Publications associées à Front side bus

General and Unified Model of the Power Flow Problem in Multiterminal AC/DC Networks

This paper proposes a generic and unified model of the power flow (PF) problem for multiterminal hybrid AC/DC networks. The proposed model is an extension of the standard AC-PF. The DC network is treated as an AC one and, in addition to the Slack, PV and P ...

IEEE Institute of Electrical and Electronics Engineers2024

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

Simone Scarfì, Qian Wang, Varun Sharma, Konstantin Androsov, Xin Chen, Rakesh Chawla, Tian Cheng, Werner Lustermann, Andromachi Tsirou, Andrea Rizzi

The Short Strip ASIC (SSA) is one of the four front-end chips designed for the upgrade of the CMS Outer Tracker for the High Luminosity LHC. Together with the Macro-Pixel ASIC (MPA) it will instrument modules containing a strip and a macro-pixel sensor sta ...

2022

Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate

Michaël Yannick Juillard

Active Debris Removal missions consist of sending a satellite in space and removing one or more debris from their current orbit. A key challenge is to obtain information about the uncooperative target. By gathering the velocity, position, and rotation of t ...

EPFL2022

Software Support for Non-Volatile Memory (NVM) Programming

David Teksen Aksun

Non-Volatile Memory (NVM) is an emerging type of memory device that provides fast, byte-addressable, and high-capacity durable storage. NVM sits on the memory bus and allows durable data structures designs similar to the in-memory equivalent ones. Expensiv ...

EPFL2021

Modeling and optimization of dedicated bus lanes space allocation in large networks with dynamic congestion

Nikolaos Geroliminis, Dimitrios Tsitsokas, Anastasios Kouvelas

Dedicated bus lanes provide a low cost and easily implementable strategy to improve transit service by minimizing congestion-related delays. Identifying the best spatial distribution of bus-only lanes in order to maximize traffic performance of an urban ne ...

2021

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

Scalable Marine Bus-Tie Switch for Switchboard Interconnections

Drazen Dujic, Gabriele Ulissi

DC power distribution systems in marine applications are in the process of being established as the preferred solution for shipboard power distribution systems. This paper presents a bus-tie switch topology for the protection of such systems. The device is ...

2020

Empirical analysis of large-scale multimodal traffic with multi-sensor data

Nikolaos Geroliminis, Nan Zheng, Hui Fu

Recent advances in the network-level traffic flow modelling provide an efficient tool for analyzing traffic performance of large-scale networks. A relationship between density and flow at the network level is developed and widely studied, namely the macros ...

PERGAMON-ELSEVIER SCIENCE LTD2020

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...

IEEE COMPUTER SOC2020

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019