Publications associées à Ordinateur central

BLADE: A BitLine Accelerator for Devices on the Edge

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon, Yasir Mahmood Qureshi

The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

2019

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

James Gonzalo King, Felix Schürmann, Michael Lee Hines, Pramod Shivaji Kumbhar, Aleksandr Ovcharenko, Jérémy Pierre Benoit Fouriaux

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually ...

2019

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Luca Benini

In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiog ...

Institute of Electrical and Electronics Engineers2017

How to Stop Under-Utilization and Love Multicores

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Iraklis Psaroudakis, Erietta Liarou

Hardware trends oblige software to overcome three major challenges against systems scalability: (1) taking advantage of the implicit/vertical parallelism within a core that is enabled through the aggressive micro-architectural features, (2) exploiting the ...

2015

Accelerating resource allocation in virtualized environments using workload classes and/or workload signatures

Dejan Novakovic, Dejan Kostic, Nedeljko Vasic, Ricardo Bianchini

Systems, methods, and apparatus for managing resources assigned to an application or service. A resource manager maintains a set of workload classes and classifies workloads using workload signatures. In specific embodiments, the resource manager minimizes ...

2013

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Martino Ruggiero, Mohamed Mostafa Sabry Aly, Pablo Garcia del Valle

On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multi-processor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from single-level on chip ...

2010

Evolution not revolution in the TCV tokamak control and acquisition system

Basil Duval, Jean-Marc Moret, Xavier Llobet, Jonathan Bryan Lister, Philippe Marmillod, Blaise Marlétaz, Pierre-François Isoz

The original TCV control system was designed in the late 1980s to be inherently network based in that all control operations were performed from X-windows terminals and the control computers were networked. Using VMS-VAX technology, the acquisition system ...

2001

Intégration énergétique de procédés discontinus à l'aide d'algorithmes génériques.

François Maréchal, Daniel Favrat, Pierre Krummenacher

This report presents a new methodological approach for the optimal design of energy integrated batch processes. The main emphasis is put on indirect and, to some extend, on direct heat exchange networks with the possibility of introducing closed or open st ...

2001

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Ordinateur central

BLADE: A BitLine Accelerator for Devices on the Edge

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

How to Stop Under-Utilization and Love Multicores

Accelerating resource allocation in virtualized environments using workload classes and/or workload signatures

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors

On the behavior of spherical and non-spherical grain assemblies, its modeling and numerical simulation

Evolution not revolution in the TCV tokamak control and acquisition system

Intégration énergétique de procédés discontinus à l'aide d'algorithmes génériques.

Graph Chatbot

Chattez avec Graph Search

On the behavior of spherical and non-spherical grain assemblies, its modeling and numerical simulation

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors

Evolution not revolution in the TCV tokamak control and acquisition system

Accelerating resource allocation in virtualized environments using workload classes and/or workload signatures

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

BLADE: A BitLine Accelerator for Devices on the Edge

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

How to Stop Under-Utilization and Love Multicores

Intégration énergétique de procédés discontinus à l'aide d'algorithmes génériques.