Concept

Intel SpeedStep

Publications associées (14)

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in t ...

New York2023

An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems

Marco Mattavelli, Catherine Dehollain, Diego Ruben Barrettino, Kerim Türe, Mustafa Besirli, Franco Maloberti

This paper presents an energy-efficient, duty-cycled, and spinning excitation bridge-to-digital converter (BDC) designed for implantable pressure sensing systems. The circuit provides the measure of the pulmonary artery pressure that is particularly releva ...

2022

A machine learning approach for power gating the FPGA routing network

Mirjana Stojilovic, Hossein Asadi

Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in the routing ...

IEEE COMPUTER SOC2019

Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

Hasene Gülperi Özsema

Twentieth century has been the golden age of semiconductor industry by achieving a high level of growth as a courtesy of developments in fabrication techniques and downscaling of the technology. Since the downscaling in current lithography technology is re ...

EPFL2017

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Institute of Electrical and Electronics Engineers2014

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Giovanni De Micheli, Siang-Yun Lee

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...

2014

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alt ...

Institute of Electrical and Electronics Engineers2013

Enabling parametric feasibility analysis in real-time calculus driven performance evaluation

Alena Simalatsar

This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature framework ...

ACM2011

A multiresolution space-time adaptive scheme for the bidomain model in electrocardiology

Ricardo Esteban Ruiz Baier

The bidomain model of electrical activity of myocardial tissue consists of a possibly degenerate parabolic PDE coupled with an elliptic PDE for the transmembrane and extracellular potentials, respectively. This system of two scalar PDEs is supplemented by ...

Wiley-Blackwell2010

Exact quantification of the sub-optimality of uniprocessor fixed-priority pre- emptive scheduling

Thomas Rothvoss

This paper examines the relative effectiveness of fixed priority pre-emptive scheduling in a uniprocessor system, compared to an optimal algorithm. The quantitative metric used in this comparison is the processor speedup factor, equivalent to the factor by ...

2009

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