Concept

Comparison of EDA software

Publications associées (42)

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Support pour l'analyse dimensionnelle en SystemC-AMS

Yusuf Leblebici, Alain Vachoux

La modélisation de systèmes hétérogènes conservatifs multi-domaines (électrique, mécanique, fluidique, etc.) requiert un moyen de vérifier que les quantités manipulées par les modèles aient des unités cohérentes. Nous présentons ici les fondations pour le ...

École Polytechnique Fédérale de Lausanne (EPFL)2009

Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits

The paper presents several improvements to our synthesis platform Xsynth that was developed targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having implemented an efficient exhaustive k-feasible cone generator it was targ ...

2009

Experimental Kohonen Neural Network Implemented in CMOS 0.18μm Technology

Rafal Tomasz Dlugosz

In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been re ...

2008

A completely scalable lumped-circuit model for horizontal and vertical HALL devices

Radivoje Popovic, Predrag Drljaca

A completely scalable lumped-circuit model for horizontal and vertical HALL devices is presented therein that can be efficiently implemented in SPICE-like EDA simulators. The model has been employed for the quantitative analysis of. a) geometrical, b) temp ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007

Horizontal Hall devices: A lumped-circuit model for EDA simulators

Radivoje Popovic, Predrag Drljaca

A completely scalable lumped-circuit model for horizontal Hall devices is presented therein that can be efficiently implemented in SPICE-like simulators. The model has been employed for the quantitative analysis of. a) geometrical, b) temperature, and c) f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007

Routing Aware Switch Hardware Customization for Networks on Chips

Giovanni De Micheli, Srinivasan Murali

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

2006

Design for Reliability of Nanometer-Scale Electronics under High Defect Density

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

High defect density exhibited by nanoelectronic technologies, and parameter variability already affecting the operation of very-deep submicron CMOS systems demand for a combination of specific solutions, focusing at each various levels of abstraction in th ...

2006

Dynamically reconfigurable bio-inspired hardware

During the last several years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modi ...

EPFL2006

VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems

This paper focuses on commonalities and differences between the two mixed-signal hardware description languages VHDL-AMS and Verilog-AMS in the case of modeling heterogeneous or multi-discipline systems. The paper has two objectives. The first one consists ...

2005

Approaches for analog VLSI simulation of the transient stability of large power networks

Christian Enz

This paper suggests several approaches for determining the transient stability of a power network by using an analog VLSI chip for simulating the system behavior. The main advantages of using this method are the much shorter computation time and lower comp ...

1999