Résistance négative

Résumé

Une résistance négative est une propriété de certains circuits électriques ou matériaux pour lesquels, sur une certaine plage, le courant qui les traverse diminue quand la tension augmente . On donne aussi le nom de résistance négative à des montages convertisseurs d'impédance négative (NIC) construits à l'aide d'amplificateurs fonctionnant avec une rétroaction positive et qui se comportent comme des « résistances actives ». Le montage se comporte comme une résistance linéaire active c'est-à-dire un générateur dont la f.e.m. serait proportionnelle au courant qui le traverse. L'intérêt c'est que, associé en série avec une résistance de même valeur, il annule les effets d'amortissement de celle ci. C'est pourquoi ce montage est utilisé dans les oscillateurs et les filtres actifs pour annuler la dissipation d'énergie provoquée par les résistances des bobines utilisées. Applications Les résistances négatives sont souvent utilisées dans les oscillateurs comme l'oscillateu

Source officielle

https://fr.wikipedia.org/wiki/R%C3%A9sistance_n%C3%A9gative

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Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device performance. As the density of number of devices increases a rise in dynamic and especially static power dissipation is ever more present, making this the biggest issue in microelectronics today. Planar silicon devices are therefore already being replaced by multiple-gate architectures and will be replaced by new channel materials and new switching mechanisms during the next 10 years. A means to decrease the threshold and supply voltage and, therefore minimizing power dissipation, is to employ devices which exhibit a steeper slope than the MOSFET limit of 60 mV/dec at room temperature. The Tunnel FET promises steep turn-on characteristics and low leakage currents as compared to MOSFETs which make it attractive for low-power operation. A great deal of work over the past years has been done to boost device performance of Tunnel FETs by combining ultimate wrap-gate architectures, incorporation of III/V materials and band engineering for hetero-tunnel junctions. The latter is seen as an ideal route towards achieving high drive currents and steep sub-threshold slopes at low supply voltages. This thesis investigates both Si Tunnel FETs and the route towards heterostructure Tunnel FETs, but also the technological challenges to achieve these device structures. The first part of this work deals with vapor-liquid-solid grown silicon in-situ doped n+-i-p nanowire Tunnel FETs in a lateral geometry, where the influence of the gate dielectric, i.e., SiO2 or HfO2, on device performance is investigated along with the study of low-temperature behavior. The devices having the strongest gate coupling due to the high-κ gate oxide HfO2 are shown to exhibit the best device performance as compared with the SiO2 gate stack. A vertical process for Si FETs is developed and improved to obtain a fully wrap-gate geometry. It is adaptable to different material systems and is the basis for the ongoing work on InAs-on-Si nanowire Tunnel FETs. Improved performance for these heterostructure devices requires in particular high doping concentrations as well as abrupt doping profiles to achieve high tunnel currents. Therefore, the second part focuses on the InAs material system and specifically the study of dopant incorporation. Doping is done in-situ using different precursors during growth. The InAs nanowires are grown in SiO2 mask openings on 〈111〉 Si substrates in a metal-organic vapor phase epitaxy process. The effect of the dopants and growth parameters on radial and vertical growth rates, wire morphology and resistivity is investigated. A method utilizing the measured Seebeck coefficient of the InAs nanowires to extract doping densities without the need of assuming a mobility value is presented. Two other reference methods where I-V characteristics of homo-and heterojunction InAs tunnel diodes are fitted by TCAD simulations confirm this approach. Doping densities ranging from 1·1017 cm−3 to 7.1·1019 cm−3 were achieved which is comparable to the highest doping concentration reported in bulk InAs. Furthermore, single vertical pn+-junctions are fabricated by growing n-type InAs nanowires on p-type InAs substrates, which show high tunnel current densities of 500 kA/cm2 at 0.3 V reverse bias. In the forward direction, negative differential resistance is obtained below 200 K, which is the characteristic feature of an Esaki diode.

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Graphene for Nanoelectronic Applications

Pankaj Sharma

During the past decade, graphene --- a monolayer of carbon atoms --- has attracted enormous interest for its use in nanoelectronic device applications. The absence of bandgap, however, has stalled its use both in logic (inability to turn off) and radio frequency (poor power gain) applications. Graphene nanoelectronic devices based on alternative and complementary approaches, which yet exploit its fundamental properties rather than trying to change them, are needed for realistic applications. The work in this thesis proposes two such alternative approaches for graphene's application. The first approach examines the use of graphene as a membrane of radio frequency (RF) nanoelectromechanical systems (NEMS) capacitive switches. Owing to its extreme thinness and exceptional mechanical properties, the use of graphene in RF NEMS switches could enable lower actuation voltages and faster switching. To evaluate its electromagnetic performance, a framework for the full-wave simulation of graphene-based RF NEMS switch is developed for the first time. A rigorous modeling approach for graphene NEMS switch taking into account both its frequency-dependent conductivity, and the variation of conductivity in the up- and down-state is presented. Our results show that RF NEMS switches based on graphene with lower sheet resistivity values can deliver superior isolation and reduced losses at micro and millimeter wave frequencies, and their isolation can also be tuned with bias voltage. An attempt is also made to characterize the fabricated switches. The second approach deals with the negative differential resistance (NDR) phenomenon in planar graphene solid-state devices. The key advantage of planar graphene-based NDR devices is their ability to exhibit NDR at higher current levels, thanks to its high mobility and saturation velocity. The observation of NDR is reported in the output characteristics of graphene field effect transistors for various channel lengths and dielectric thicknesses at room temperature. The transistors are fabricated using chemical vapor deposition graphene with a top gate oxide down to 2.5 nm of equivalent oxide thickness. To understand the NDR phenomenon in graphene transistors, we perform extensive theoretical studies based on drift-diffusion model. This understanding allows us to design a novel graphene circuit which shows enhanced NDR characteristics and is more relevant for applications. Finally, the potential of this graphene NDR circuit is evaluated for RF reflection amplifiers application.

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Intrinsic switching in Si-doped HfO2: A study of Curie-Weiss law and its implications for negative capacitance field-effect transistor

Matteo Cavalieri, Carlotta Gastaldi, Mihai Adrian Ionescu, Sadegh Kamaei Bahmaei, Teodor Rosca, Ali Saeidi, Igor Stolichnov

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applications in which a ferroelectric gate stack exploits a stabilized negative capacitance regime capable to differentially amplify the surface potential in a metal-oxide-semiconductor FET structure, resulting in the improvement of the subthreshold swing and overdrive. In a number of relevant studies of negative capacitance, intrinsic (thermodynamic) switching is assumed, since alternative switching scenarios predict undesirable hysteretic responses in logic devices. However, there is little support from the experimental data showing that the polarization reversal in HfO2-based ferroelectrics is really driven by the intrinsic switching mechanism. In this work, polarization hysteresis loops are measured over wide temperature ranges on polycrystalline Si-doped HfO2 (Si:HfO2) capacitors. The analysis herein, which is based on the classic Landau-Ginzburg-Devonshire theory, yields the temperature-dependent dielectric susceptibility values, which fit the Curie-Weiss law. The extrapolated Curie temperature value is in line with the data obtained for other HfO2-based ferroelectrics using different techniques. The work also illustrates a method to evaluate the ferroelectric equivalent negative capacitance value and range of voltages, aiming at study and optimization of a stabilized negative capacitance FET. This study indicates that the intrinsic switching provides an adequate description of the polarization hysteresis in Si:HfO2 films. This confirms the usability of hafnia-based ferroelectrics for negative capacitance logic devices, and the important role that the intrinsic mechanism plays in the dielectric response of these materials.

AMER INST PHYSICS2021

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EPFL2015

Intrinsic switching in Si-doped HfO2: A study of Curie-Weiss law and its implications for negative capacitance field-effect transistor

Matteo Cavalieri, Carlotta Gastaldi, Mihai Adrian Ionescu, Sadegh Kamaei Bahmaei, Teodor Rosca, Ali Saeidi, Igor Stolichnov

AMER INST PHYSICS2021