Concept

PowerPC

Publications associées (73)

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Martino Ruggiero, Mohamed Mostafa Sabry Aly, Pablo Garcia del Valle

On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multi-processor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from single-level on chip ...

2010

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

Seyed Armin Tajalli, Yusuf Leblebici

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed techniq ...

DATE2010

NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in ...

2009

The Semantics of Progress in Lock-Based Transactional Memory

Rachid Guerraoui, Michal Kapalka

Transactional memory (TM) is a promising paradigm for concurrent programming. Whereas the number of TM implementations is growing, however, little research has been conducted to precisely define TM semantics, especially their progress guarantees. This pape ...

ACM2009

Finite Rate of Innovation sampling techniques for embedded UWB devices.

Yann Barbotin

This report studies the applicability of Finite Rate of Innovation (FRI) algorithms to UltraWide Band (UWB) communications, more precisely in the scope of Low Power Body Area Networks (LP-BAN ). Three main issues are studied and given proposed solutions. F ...

2009

The Semantics of Progress in Lock-Based Transactional Memory

Rachid Guerraoui, Michal Kapalka

2008

Smart camera with embedded co-processor: a postal sorting application

Marco Mattavelli, Romuald Mosqueron, Julien Dubois

This work describes an image acquisition and processing system based on a new co-processor architecture designed for CMOS sensor imaging. The platform permits to configure a wide variety of acquisition modes (random region acquisition, variable image size, ...

2008

Power and Reliability Management of SoCs

Giovanni De Micheli

Today's embedded systems integrate multiple IP cores for processing, communication, and sensing on a single die as systems-on-chip (SoCs). Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature have made reli ...

2007

NoC Design and Implementation in 65 nm Technology

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

2007

Optimization of Dynamic Data Structures in Multimedia Embedded Systems Using Evolutionary Computation

David Atienza Alonso

Embedded consumer devices are increasing their capabilities and can now implement new multimedia applications reserved only for powerful desktops a few years ago. These applications share complex and intensive dynamic memory use. Thus, dynamic memory optim ...

ACM2007

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