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Intel Core

Publications associées (295)

Generic construction of consensus algorithms for benign and Byzantine faults

André Schiper, Zarko Milosevic, Olivier Rütti

The paper proposes a generic consensus algorithm that highlights the basic and common features of known consensus algorithms. The parameters of the generic algorithm encapsulate the core differences between various consensus algorithms, including leader-ba ...

2010

Run-Time Mapping for Dynamically-Added Applications in Reconfigurable Embedded Systems

David Atienza Alonso, Ivan Beretta

The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in terms of hardware platforms and design methodologies. Dynamic reconfiguration can be exploited to increase the flexibility of the system and to implement mu ...

IEEE Press2009

TMunit: Testing Transactional Memories

Vincent Gramoli, Pascal Felber

Transactional memory (TM) is expected to become a widely used parallel programming paradigm for multi-core architectures. To reach this goal, we need tools that do not only help develop TMs, but also test them and evaluate them on a wide range of workloads ...

2009

Single-Gate 320-to-8x40 Gb/s Demultiplexing

Camille Sophie Brès

The first experimental demonstration of 320Gb/s demultiplexing to eight simultaneous always-on 40Gb/s tributaries with near-zero latency is reported. Error-free demultiplexing is achieved by a single parametric processor operating in copy-and-sample mode o ...

2009

Shore-MT: A Scalable Storage Manager for the Multicore Era

Anastasia Ailamaki, Babak Falsafi, Frederick Ryan Johnson, Ippokratis Pandis

Database storage managers have long been able to efficiently handle multiple concurrent requests. Until recently, however, a computer contained only a few single-core CPUs, and therefore only a few transactions could simultaneously access the storage manag ...

ACM2009

Concurrent Programming Paradigms, A Comparison in Scala

Rachid Guerraoui, Martin Odersky, Mohsen Lesani

There is a rapid rise of multi-cores in recent hardware architectures. To exploit computational power of multi-core architectures, software should shift to be as concurrent as possible; and therefore should have concurrency control mechanisms. There are di ...

2009

Micro Fluxgate Sensor with Cascaded Planar Ring Cores

Pavel Kejik, Ozge Zorlu

In this paper, we present a new microfabricated fluxgate sensor structure having cascaded planar rings as the ferromagnetic core. A circular magnetic excitation is provided with a rod passing through the FeNi rings as a sewing thread. Planar coils placed u ...

2009

Optimizing Transactions for Captured Memory

Aleksandar Dragojevic

In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is memory allocated inside a transaction, which cannot escape (i.e., is capture ...

ACM2009

Through Silicon Via-Based Grid for Thermal Control in 3D Chips

David Atienza Alonso, Yusuf Leblebici, Arvind Raj Mahankali Sridhar, José Luis Ayala Rodrigo, Vinod Pangracious

3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communica ...

Springer2009

Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last- level cache for multicore processors. The large working sets favor a shared cache design that maximizes the ag ...

2009

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