Publications associées à Instruction-level parallelism

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, Beatrice Shokry Samir Shokry, Wei Hu

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

2024

Imprecise Store Exceptions

Babak Falsafi, Mathias Josef Payer, Yuanlong Li, Siddharth Gupta, Yunho Oh, Qingxuan Kang, Abhishek Bhattacharjee

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

ACM2023

FISHFUZZ: Catch Deeper Bugs by Throwing Larger Nets

Mathias Josef Payer, Flavio Toffalini, Han Zheng, Yuqing Zhang, Jiayuan Zhang

Fuzzers effectively explore programs to discover bugs. Greybox fuzzers mutate seed inputs and observe their execution. Whenever a seed reaches new behavior (e.g., new code or higher execution frequency), it is stored for further mutation. Greybox fuzzers d ...

Berkeley2023

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

David Atienza Alonso, Giovanni Ansaloni, Grégoire Axel Eggermann, Marco Antonio Rios

State-of-the-art Artificial Intelligence (AI) algorithms, such as graph neural networks and recommendation systems, require floating-point computation of very large matrix multiplications over sparse data. Their execution in resource-constrained scenarios, ...

2023

Improving K-means Clustering Using Speculation

Anastasia Ailamaki, Viktor Sanca, Eleni Zapridou, Stefan Igescu

K-means is one of the fundamental unsupervised data clustering and machine learning methods. It has been well studied over the years: parallelized, approximated, and optimized for different cases and applications. With increasingly higher parallelism leadi ...

2023

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Ayatallah Ahmed Gamal Kamal Elakhras

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

IEEE COMPUTER SOC2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Carmine Rizzi

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022

The dynamic stall dilemma for vertical-axis wind turbines

Karen Ann J Mulleners, Sébastien Le Fouest

Vertical-axis wind turbines (VAWT) are excellent candidates to complement traditional wind turbines and increase the total wind energy capacity. Development of VAWT has been hampered by their low efficiency and structural unreliability, which are related t ...

PERGAMON-ELSEVIER SCIENCE LTD2022

Micro-architectural analysis of in-memory OLTP: Revisited

Anastasia Ailamaki, Danica Porobic, Utku Sirin

Micro-architectural behavior of traditional disk-based online transaction processing (OLTP) systems has been investigated extensively over the past couple of decades. Results show that traditional OLTP systems mostly under-utilize the available micro-archi ...

2021

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Instruction-level parallelism

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Imprecise Store Exceptions

FISHFUZZ: Catch Deeper Bugs by Throwing Larger Nets

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

Improving K-means Clustering Using Speculation

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Real-Time Nonlinear Model Predictive Control for Fast Mechatronic Systems

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

The dynamic stall dilemma for vertical-axis wind turbines

Micro-architectural analysis of in-memory OLTP: Revisited

Graph Chatbot

Chattez avec Graph Search

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

Real-Time Nonlinear Model Predictive Control for Fast Mechatronic Systems

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Imprecise Store Exceptions

Micro-architectural analysis of in-memory OLTP: Revisited

FISHFUZZ: Catch Deeper Bugs by Throwing Larger Nets

Improving K-means Clustering Using Speculation

The dynamic stall dilemma for vertical-axis wind turbines