Publications associées à Cycles per instruction

Fast cross-correlation based wrist vein recognition algorithm with rotation and translation compensation

Sébastien Marcel, André Anjos, Teodors Eglitis

Most of the research on vein biometrics addresses the problems of either palm or finger vein recognition with a considerably smaller emphasis on wrist vein modality. This paper paves the way to a better understanding of capabilities and challenges in the f ...

2018

Okapi : Causally Consistent Geo-Replication Made Faster, Cheaper and More Available

Willy Zwaenepoel, Diego Didona, Kristina Spirovska

Okapi is a new causally consistent geo-replicated key-value store. Okapi leverages two key design choices to achieve high performance. First, it relies on hybrid logical/physical clocks to achieve low latency even in the presence of clock skew. Second, Oka ...

2017

Unified prefetching into instruction cache and branch target buffer

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction blo ...

2017

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

This article presents ESTIMA, an easy-to-use tool for extrapolating the scalability of in-memory applications. ESTIMA is designed to perform a simple yet important task: Given the performance of an application on a small machine with a handful of cores, ES ...

2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

This paper presents ESTIMA, an easy-to-use tool for extrapolating the scalability of in-memory applications. ESTIMA is designed to perform a simple, yet important task: given the performance of an application on a small machine with a handful of cores, EST ...

ACM Press2016

Establishing a base of trust with performance counters for enterprise workloads

Willy Zwaenepoel, Andrzej Pawel Nowak

Understanding the performance of large, complex enterprise-class applications is an important, yet nontrivial task. Methods using hardware performance counters, such as profiling through event-based sampling, are often favored over instrumentation for anal ...

2015

BuMP: Bulk Memory Access Prediction and Streaming

Babak Falsafi, Boris Robert Grot, Stavros Volos, Javier Picorel Obando

With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As th ...

2014

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Cycles per instruction

Fast cross-correlation based wrist vein recognition algorithm with rotation and translation compensation

Okapi : Causally Consistent Geo-Replication Made Faster, Cheaper and More Available

Unified prefetching into instruction cache and branch target buffer

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Establishing a base of trust with performance counters for enterprise workloads

BuMP: Bulk Memory Access Prediction and Streaming

ADDICT: Advanced Instruction Chasing for Transactions

Graph Chatbot

Chattez avec Graph Search

Fast cross-correlation based wrist vein recognition algorithm with rotation and translation compensation

Unified prefetching into instruction cache and branch target buffer

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

ADDICT: Advanced Instruction Chasing for Transactions

Okapi : Causally Consistent Geo-Replication Made Faster, Cheaper and More Available

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Establishing a base of trust with performance counters for enterprise workloads

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

BuMP: Bulk Memory Access Prediction and Streaming