Power management | EPFL Graph Search

Power management is a feature of some electrical appliances, especially copiers, computers, computer CPUs, computer GPUs and computer peripherals such as monitors and printers, that turns off the power or switches the system to a low-power state when inactive. In computing this is known as PC power management and is built around a standard called ACPI, this supersedes APM. All recent computers have ACPI support. Motivations PC power management for computer systems is desired for many reasons, particularly:

Reduce overall energy consumption
Prolong battery life for portable and embedded systems
Reduce cooling requirements
Reduce noise
Reduce operating costs for energy and cooling

Lower power consumption also means lower heat dissipation, which increases system stability, and less energy use, which saves money and reduces the impact on the environment. Processor level techniques The power management for microprocessors can be done over the whole processor,

High-Speed Wireline Link Design

Hazar Yüksel

High-speed serial links are a crucial application of semiconductor technology and have been the enabler of the scaling of computing systems. The increasing data-rate requirements of these links have only been partially satisfied by advancements in process technologies. Implementing serial links operating at a data rate of more than 25 Gb/s thus requires constantly inventing smarter algorithms, architectures, power-management techniques, and new standards. The Viterbi algorithm (VA), an attractive solution for symbol detection in the presence of intersymbol interference (ISI) and noise, minimizes the error probability in detecting the whole symbol sequence, instead of a single symbol as in decision-feedback equalization. The bit-error-rate (BER) performance of the VA is thus better than that of symbol-by-symbol detectors because the VA does not cancel the ISI, but rather uses the information embedded therein to maximize the reliability of its decisions. However, implementing a maximum-likelihood sequence detector (MLSD) realizing the VA may be prohibitive because design specifications regarding area, latency, power consumption, and speed may not be satisfied concurrently. Suboptimal solutions, such as feed-forward and decision-feedback equalizers (DFEs), may therefore be chosen instead of MLSDs due to their lower implementation complexity. A reduced-state sequence detector (RSSD) reduces the implementation complexity of the MLSD with negligible performance degradation by exploiting set-partitioning principles and embedded per-survivor decision feedback. A sliding-block or systolic-array Viterbi detector (VD) breaks the speed bottleneck in sequence-detector implementations by parallelizing the operation of the VA. In this thesis, we implement a 56-Gb/s four-level pulse-amplitude-modulation (4-PAM) DFE to demonstrate the feasibility of a multi-level analog-to-digital-converter (ADC)-based symbol-by-symbol detector in terms of achievable area, BER, energy-efficiency, latency, and speed figures comparable to those of analog solutions. Furthermore, to improve the BER figures, we implement a 25.6-Gb/s 4-PAM reduced-state sliding-block VD to demonstrate the feasibility of a multi-level sequence detector in terms of achievable area, energy-efficiency, latency, and speed figures comparable to those of symbol-by-symbol detectors. Moreover, we develop a sliding-block VA with optimized unequal synchronization and survivor path memory lengths to reduce its implementation complexity, latency, and power consumption. An increase in speed is thereby achieved at the same implementation complexity, BER, latency, and power consumption. We then develop a novel VD with embedded per-survivor decision feedback, whose longest path contains only one adder, to increase its speed significantly. Next, we propose a concatenated-coding scheme using an outer Reed—Solomon code and a four-dimensional (4-D) 5-PAM inner trellis-coded-modulation (TCM) scheme to achieve signal-to-noise-ratio gains without bandwidth expansion. Finally, we implement a 70-Gb/s 4-D 5-PAM systolic-array TCM decoder with eight states, which includes an inverse Tomlinson—Harashima precoder, to demonstrate the feasibility of a multi-level ADC-based sequence decoder in terms of achievable speed figures comparable to those of sequence detectors.

EPFL2017

Making Cluster Applications Energy-Aware

Martin Barisits, Dejan Kostic, Vincent Salzgeber, Nedeljko Vasic

Power consumption has become a critical issue in large scale clusters. Existing solutions for addressing the servers' energy consumption suggest ``shrinking'' the set of active machines, at least until the more power-proport-ional hardware devices become available. This paper demonstrates that leveraging the sleeping state, however, may lead to unacceptably poor performance and low data availability if the distributed services are not aware of the power management's actions. Therefore, we present an architecture for cluster services in which the deployed services overcome this problem by actively participating in any action taken by the power management. We propose, implement, and evaluate modifications for the Hadoop Distributed File System and the MapReduce clone that make them capable of operating efficiently under limited power budgets.

2009

A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems

Yao Shi

We present a fully integrated energy reservoir unit using a counter flow method for peak power delivery in space-constrained sensor systems. Recent advances in circuits have enabled significant reduction in the size of wireless systems such as implantable biomedical devices. As a consequence, the batteries integrated in these systems have also shrunk, resulting in high internal resistances (~10 kQ). However, the peak current requirement of power-hungry components such as radios remains in the milliwatt range and hence cannot directly be supplied from the battery. Therefore, an energy reservoir with high output power but small size is required. We present an efficient energy reservoir that dynamically reconfigures a storage capacitor array using a so-called counter flow approach. By creating a voltage gradient on capacitor arrays and moving the capacitors along the slope of the gradient, the supply voltage can be maintained while the energy stored in the reservoir is delivered efficiently to the load. The counter flow energy reservoir delivers 65% of stored energy before recharging is needed which allows up to a 12× reduction in overall capacitor size compared with our implementation of the previous method. The design supplies up to 13.6-mW output power for 1 μs. We demonstrate the proposed concept with a pulsed radio, showing an 11.5× increase in pulse length compared with the previous method.

IEEE2017

High-Speed Wireline Link Design

Hazar Yüksel

EPFL2017