Publications associées à Clock gating

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Adam Shmuel Teman, Andrea Bonetti, Nicholas Alexander Preyss

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017

Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

This paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signa ...

2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging

Edoardo Charbon, Claudio Bruschini, Francesco Regazzoni, Samuel Burri, François Eric Powolny

This paper presents our work on a 65k pixel single-photon avalanche diode (SPAD) based imaging sensor realized in a 0.35 mu m standard CMOS process. At a resolution of 512 by 128 pixels the sensor is read out in 6.4ps to deliver over 150k monochrome frames ...

Spie-Int Soc Optical Engineering2014

Dynamic Fine-Grained Scheduling for Energy-Efficient Main-Memory Queries

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Iraklis Psaroudakis, Erietta Liarou

Power and cooling costs are some of the highest costs in data centers today, which make improvement in energy efficiency crucial. Energy efficiency is also a major design point for chips that power whole ranges of computing devices. One important goal in t ...

2014

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Jian Zhang

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar trans ...

Ieee-Inst Electrical Electronics Engineers Inc2013

AlN-Capped AlInN/GaN High Electron Mobility Transistors with 4.5W/mm Output Power at 40 GHz

Nicolas Grandjean, Jean-François Carlin, Lorenzo Lugani

We report the characterization of GaN high electron mobility transistors (HEMTs) using a new AlN-capped AlInN/GaN epilayer structure developed to achieve high current densities and reduced gate leakage currents. Devices with gate lengths of 75 and 200 nm a ...

Iop Publishing Ltd2013

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Giovanni De Micheli, Xifan Tang, Vasileios Pavlidis, Hu Xu, Wayne Burleson

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

Institute of Electrical and Electronics Engineers2013

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Clock gating

Adaptive Receiver Design for High Speed Optical Communication

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Signaling in 3-D integrated circuits, benefits and challenges

A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging

Dynamic Fine-Grained Scheduling for Energy-Efficient Main-Memory Queries

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

AlN-Capped AlInN/GaN High Electron Mobility Transistors with 4.5W/mm Output Power at 40 GHz

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Graph Chatbot

Chattez avec Graph Search

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Dynamic Fine-Grained Scheduling for Energy-Efficient Main-Memory Queries

Adaptive Receiver Design for High Speed Optical Communication

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Signaling in 3-D integrated circuits, benefits and challenges

A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging

AlN-Capped AlInN/GaN High Electron Mobility Transistors with 4.5W/mm Output Power at 40 GHz

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs