Publications associées à Multi-chip module

Fast Thermal Simulation of 2D/3D Integrated Circuits Exploiting Neural Networks and GPUs

David Atienza Alonso, Arvind Raj Mahankali Sridhar, Martino Ruggiero, Alessandro Vincenzi

Heat removal is one of the major challenges faced in developing the new generation of high density integrated circuits. Future design technologies strongly depend on the availability of efficient means for thermal modeling and analysis. These thermal model ...

ACM and IEEE Press2011

A Discrete-Components Impulse-Radio Ultrawide-Band (IR-UWB) Transmitter

Catherine Dehollain, Edmund James Colli-Vignarelli

We describe an impulse-radio ultra-wideband (IR-UWB) transmitter made with off-the-shelf discrete components. It was initially designed to be used in a UWB testbed for measurement and algorithm validation purposes. There already exist several versions of a ...

Institute of Electrical and Electronics Engineers2011

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

David Atienza Alonso, Ivan Beretta

Nowadays, multi-core Systems-on-Chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platfo ...

Institute of Electrical and Electronics Engineers2011

Achieving high-throughput State Machine Replication in multi-core systems

André Schiper, Nuno Filipe de Sousa Santos

State machine replication is becoming an increasingly popular technique among online services to ensure fault-tolerance using commodity hardware. This has led to a renewed interest in its throughput, as these services have typically a large number of users ...

2011

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Yusuf Leblebici, Fengda Sun

Surface-tension-driven self-alignment (SA) is a promising technique for heterogeneous die-level stacking. Multiple dies can be manipulated in parallel at minimal cost. A defined amount of water present between the die and a carrier substrate is used to ali ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Methodology for the Hardware/Software Co-Design of Dataflow Programs

Marco Mattavelli, Ghislain Roquier, Richard Thavot

New generations of multi-core processors and reconfigurable hardware platforms are expected to provide a dramatic increase of processing capabilities. However, one obstacle for exploiting all the promises of such new platforms is the legacy of current appl ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Methodology For The Hardware/Software Co-Design Of Dataflow Programs

Marco Mattavelli, Ghislain Roquier, Richard Thavot

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Giovanni De Micheli, Shashi Kanth Bobba, Thomas Ernst

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contac ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Giovanni De Micheli, Babak Falsafi, Ciprian Seiculescu, Stavros Volos, Naser Khosro Pour

Manycore chips are emerging as the architecture of choice to provide power-scalability and improve performance while riding the Moore’s law. On-chip interconnects are increasingly playing a pivotal role in power- and performance- scalability of such microa ...

2011

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Multi-chip module

Fast Thermal Simulation of 2D/3D Integrated Circuits Exploiting Neural Networks and GPUs

A Discrete-Components Impulse-Radio Ultrawide-Band (IR-UWB) Transmitter

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

Achieving high-throughput State Machine Replication in multi-core systems

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Methodology for the Hardware/Software Co-Design of Dataflow Programs

Methodology For The Hardware/Software Co-Design Of Dataflow Programs

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Graph Chatbot

Chattez avec Graph Search

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

Methodology for the Hardware/Software Co-Design of Dataflow Programs

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Fast Thermal Simulation of 2D/3D Integrated Circuits Exploiting Neural Networks and GPUs

Achieving high-throughput State Machine Replication in multi-core systems

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Methodology For The Hardware/Software Co-Design Of Dataflow Programs

A Discrete-Components Impulse-Radio Ultrawide-Band (IR-UWB) Transmitter

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips