Skylake

Résumé

Skylake est la micro-architecture de processeurs x86 d'Intel qui succède à la micro-architecture Haswell à partir d'août 2015. Avec cette nouvelle micro-architecture, Intel abandonne sa traditionnelle stratégie tic-tac. En effet, la firme a connu quelques difficultés pour le passage à la gravure en , et prend encore du retard pour la gravure en . Cette architecture est donc déclinée en de bien plus nombreuses familles qu'à l'accoutumée. La famille de microprocesseurs Cannon Lake gravée en est prévue pour 2018, et sera toujours basée sur la micro-architecture Skylake. Chez Intel, le inaugure la lithographie extrême ultraviolet, pour succéder aux processus lithographiques classiques à immersion à laser à fluorure d'argon d’une longueur d'onde de . La chronologie des familles de microprocesseurs cités est donc la suivante :

micro-architecture Haswell : ** famille de processeurs Haswell, gravés en , depuis ** famille de processeurs Broadwell, gravés en , depuis
micro-architec

Source officielle

https://fr.wikipedia.org/wiki/Skylake

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Publications associées (4)

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Babak Falsafi, Sotiria Fytraki, Boris Robert Grot, Yusuf Onur Koçberber, Evangelos Vlachos

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recurring theme in recent work is the use of hardware-assisted filtering so as to elide costly software analysis. This work generalizes and extends prior point solutions into a programmable filtering accelerator affording vast flexibility and at-speed event filtering. The pipelined microarchitecture of the accelerator affords a peak filtering rate of one application event per cycle, which suffices to keep up with an aggressive OoO core running the monitored application. A unique feature of the proposed design is the ability to dynamically resolve dependencies between unfilterable events and subsequent events, eliminating data-dependent stalls and maximizing accelerator’s performance. Our evaluation results show a monitoring slowdown of just 1.2-1.8x across a diverse set of monitoring tools.

2014

Chargement

Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture

Sandhya Dwarkadas

We describe the design, analysis, and performance of an on-line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MCD microarchitecture allows the frequency/voltage of micrprocessor regions to be adjusted independently and dynamically, allowing enery savings when the frequency of some regions can be reduced without significantly impacting performance. Our algorithm achieves on average a 19.0% reduction in Energy Per Instriction (EPI), a 3.2% increase in Cycles Per Instruction (CPI), a 16.7% improvement in Energy–Delay Product, and a Power Savings to Performance Degradation ratio of 4.6. Traditional frequency/voltage scaling techniques which apply reductions globally to a fully synchronous processor achieve a Power Savings to Performance Degradation ratio of only 2–3. Our Energy–Delay Product improvement is 85.5% of what has been achieved using an off–line algorithm. These results were achieved using a broad range of applications from the MediaBench, Olden, and Spec2000 benchmark suites using an algorithm we show to require minimal hardware resources.

2002

Chargement

We analyze an Alpha 21264-like Globally–Asynchronous, Locally–Synchronous (GALS) processor organized as a Multiple Clock Domain (MCD) microarchitecture and identify the architectural features of the processor that influence the limited performance degradation measured. We show that the out-oforder superscalar execution features of a processor, which allow traditional instruction execution latency to be hidden, are the same features that reduce the performance degradation impact of the synchronization costs of an MCD processor. In the case of our Alpha 21264-like processor, up to 94% of the MCD synchronization delays are hidden and do not impact overall performance. In addition, we show that by adding out-of-order superscalar execution capabilities to a simpler microarchitecture, such as an Intel StrongARM-like processor, as much as 62% of the performance degradation caused by synchronization delays can be eliminated.

2004

Chargement

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