Concept

Serial Peripheral Interface

Publications associées (32)

FPGA-Assisted Deterministic Routing for FPGAs

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The oppo ...

2018

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust, Chen Cao, Thierry Barailler

This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone (AMT) signaling for chip-to-chip communication. Multi-tone single-sideband (SSB) signaling scheme is proposed in TRX architecture in ord ...

Ieee-Inst Electrical Electronics Engineers Inc2017

An Out-of-Order Load-Store Queue for Spatial Computing

Paolo Ienne, Lana Josipovic, Philip Brisk

The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and ensuring ap ...

Assoc Computing Machinery2017

Practical control methods for vacuum driven soft actuator modules

Jamie Paik, Matthew Aaron Robertson

Vacuum-powered Soft Pneumatic Actuator (VSPA) Modules have been described to afford advantages for rapid development of reconfigurable, multi-DoF soft pneumatic robots powered by vacuum by reducing their logistical complexity, however they also present new ...

2017

Analysis, Optimization, and Modeling of Analog Multi-Tone Serial Data Transceivers

Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust

This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, ...

2017

A Fully-Digital Spectrum Shaping Signaling for Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Memory Interfaces

Seyed Armin Tajalli, Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust

An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rath ...

Ieee2016

Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications

Mohammad Amin Shokrollahi, Anant Pratap Singh

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are ...

2016

Cyber-attack on Packet-Based Time Synchronization Protocols: the Undetectable Delay Box

Jean-Yves Le Boudec, Aswin Suresh, Sergio Barreto Andrade

We present a cyber-attack on packet-based time synchronization protocols (PBTSP) with high-accuracy requirements. The cyber-attack is undetectable from the PBTSP's perspective and exploits a vulnerability that is in the nature of all PBTSPs. It can be succ ...

Ieee2016

Architectural Modeling of a Multi-Tone/Single-Sideband Serial Link Transceiver for Lossy Wireline Data Links

Yusuf Leblebici, Gain Kim

This paper presents a serial link transceiver (TRX) architecture that enables high-speed data transmission over a lossy backplane channel without the presence of equalization circuits. The proposed architecture employs multi-tone signaling to reduce inter- ...

Ieee2016

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