Hardware architecture | EPFL Graph Search

In engineering, hardware architecture refers to the identification of a system's physical components and their interrelationships. This description, often called a hardware design model, allows hardware designers to understand how their components fit into a system architecture and provides to software component designers important information needed for software development and integration. Clear definition of a hardware architecture allows the various traditional engineering disciplines (e.g., electrical and mechanical engineering) to work more effectively together to develop and manufacture new machines, devices and components. Hardware is also an expression used within the computer engineering industry to explicitly distinguish the (electronic computer) hardware from the software that runs on it. But hardware, within the automation and software engineering disciplines, need not simply be a computer of some sort. A modern automobile runs vastly more software than the Apollo s

Rigorous system level modeling and analysis of mixed HW/SW systems

Kai Huang, Joseph Sifakis

A grand challenge in complex embedded systems design is developing methods and tools for modeling and analyzing the behavior of an application software running on multicore or distributed platforms. We propose a rigorous method and a tool chain that allows to obtain a faithful model representing the behavior of a mixed hardware/software system from a model of its application software and a model of its underlying hardware architecture. The system model can be simulated and analyzed for validation of both functional and extra-functional properties. The tool chain uses DOL (Distributed Operation Layer) as the frontend for specifying the application software and hardware architecture, and BIP (Behavior Interaction Priority) as the modeling and analysis framework. It is illustrated through the construction of system models of MJPEG and MPEG2 decoder applications running on MPARM, a multicore architecture.

IEEE2011

A Spherical Multi-camera System with Real-time Omnidirectional Video Acquisition Capability

Hossein Afshari, Yusuf Leblebici, Vladan Popovic, Alexandre Schmid

A multi-camera system inspired from the visual system of flying insects is introduced which is referred to as the Panoptic camera. In the Panoptic system each camera is mounted over a hemispherical geometry and has its own vision of surrounding and distinct focal direction. The Panoptic device finds application in the area of omnidirectional vision and 3D imaging. A systematic approach is presented for the coverage analysis and design guidelines of the Panoptic device. The presented approach enables the construction of arbitrary multi-camera systems based on the Panoptic principle. An implemented hardware architecture based on FPGA is introduced which is capable of real-time omnidirectional vision reconstruction. The implemented hardware is capable of live video streaming at a rate of 6.25M pixels per second and a maximum image resolution of 32M pixels per FPGA board.

Institute of Electrical and Electronics Engineers2012

Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography

Subhadeep Banik, Hamid Nejatollahi, Francesco Regazzoni

The advent of the quantum computer makes current public-key infrastructure insecure. Cryptography community is addressing this problem by designing, efficiently implementing, and evaluating novel public-key algorithms capable of withstanding quantum computational power. Governmental agencies, such as NIST, are promoting standardization of quantum-resistant algorithms that is expected to run for 7 years. Several modern applications must maintain permanent data secrecy; therefore, they ultimately require the use of quantum-resistant algorithms. Because algorithms are still under scrutiny for eventual standardization, the deployment of the hardware implementation of quantum-resistant algorithms is still in early stages. In this article, we propose a methodology to design programmable hardware accelerators for lattice-based algorithms, and we use the proposed methodology to implement flexible and energy efficient post-quantum cache-based accelerators for NewHope, Kyber, Dilithium, Key Consensus from Lattice (KCL), and R.EMBLEM submissions to the NIST standardization contest. To the best of our knowledge, we propose the first efficient domain-specific, programmable cache-based accelerators for lattice-based algorithms. We design a single accelerator for a common kernel among various schemes with different kernel sizes, i.e., loop count, and data types. This is in contrast to the traditional approach of designing one special purpose accelerators for each scheme. We validate our methodology by integrating our accelerators into an HLS-based SoC infrastructure based on the X86 processor and evaluate overall performance. Our experiments demonstrate the suitability of the approach and allow us to collect insightful information about the performance bottlenecks and the energy efficiency of the explored algorithms. Our results provide guidelines for hardware designers, highlighting the optimization points to address for achieving the highest energy minimization and performance increase. At the same time, our proposed design allows us to specify and execute new variants of lattice-based schemes with superior energy efficiency compared to the main application processor without changing the hardware acceleration platform. For example, we manage to reduce the energy consumption up to 2.1x and energy-delay product (EDP) up to 5.2x and improve the speedup up to 2.5x.

ASSOC COMPUTING MACHINERY2020

Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography

Subhadeep Banik, Hamid Nejatollahi, Francesco Regazzoni

ASSOC COMPUTING MACHINERY2020