Broadwell is the fifth generation of the Intel Core Processor. It is Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle as the next step in semiconductor fabrication. Like some of the previous tick-tock iterations, Broadwell did not completely replace the full range of CPUs from the previous microarchitecture (Haswell), as there were no low-end desktop CPUs based on Broadwell. Some of the processors based on the Broadwell microarchitecture are marketed as "5th-generation Core" i3, i5 and i7 processors. This moniker is however not used for marketing of the Broadwell-based Celeron, Pentium or Xeon chips. This microarchitecture also introduced the Core M processor branding. Broadwell is the last Intel platform on which Windows 7 is supported by either Intel or Microsoft; however, third-party hardware vendors have offered limited Windows 7 support on more recent platforms. Broadwell's H and C variants are used in conjunction with Intel 9 Series chipsets (Z97, H97 and HM97), in addition to retaining backward compatibility with some of the Intel 8 Series chipsets. Broadwell has been launched in three major variants: BGA package: Broadwell-Y: system on a chip (SoC); 4.5 W and 3.5 W thermal design power (TDP) classes, for tablets and certain ultrabook-class implementations. GT2 GPU was used, while maximum supported memory is 8 GB of LPDDR3-1600. These were the first chips to roll out, in Q3/Q4 2014. At Computex 2014, Intel announced that these chips would be branded as Core M. TSX instructions are disabled in this series of processors because a bug that cannot be fixed with a microcode update exists. Broadwell-U: SoC; two TDP classes - 15 W for 2+2 and 2+3 configurations (two cores with a GT2 or GT3 GPU) as well as 28 W for 2+3 configurations. Designed to be used on motherboards with the PCH-LP chipset for Intel's ultrabook and NUC platforms. Maximum supported is up to 16 GB of DDR3 or LPDDR3 memory, with DDR3-1600 and LPDDR3-1867 as the maximum memory speeds.
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Paolo Ienne, Mikhail Asiatici, Damian Maiorano