Junction Field Effect Transistor

Résumé

Un transistor de type JFET (Junction Field Effect Transistor) est un transistor à effet de champ dont la grille est directement en contact avec le canal. On distingue les JFET avec un canal de type N, et ceux avec un canal de type P. Histoire Le JFET est né le lorsque William Shockley dévoile que son équipe du laboratoire Bell a mis au point un tout nouveau transistor à jonction. Types et Symboles De même que l'on distingue deux types de transistors bipolaires, les NPN et les PNP, l'on distingue aussi deux types de transistors FET à jonction (JFET) :

les JFET canal N, Le JFET canal N est le plus utilisé (comme d'ailleurs le transistor bipolaire NPN), son symbole est indiqué ci-dessous dans les schémas de mise en œuvre,
les JFET canal P, Le symbole du JFET canal P est identique, à part la flèche qui change de sens.

Comme pour les transistors bipolaires, on a le choix entre un grand nombre de modèles, selon la puissance mise en œuvre et la bande de fréquence

Source officielle

https://fr.wikipedia.org/wiki/Junction_Field_Effect_Transistor

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Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device performance. As the density of number of devices increases a rise in dynamic and especially static power dissipation is ever more present, making this the biggest issue in microelectronics today. Planar silicon devices are therefore already being replaced by multiple-gate architectures and will be replaced by new channel materials and new switching mechanisms during the next 10 years. A means to decrease the threshold and supply voltage and, therefore minimizing power dissipation, is to employ devices which exhibit a steeper slope than the MOSFET limit of 60 mV/dec at room temperature. The Tunnel FET promises steep turn-on characteristics and low leakage currents as compared to MOSFETs which make it attractive for low-power operation. A great deal of work over the past years has been done to boost device performance of Tunnel FETs by combining ultimate wrap-gate architectures, incorporation of III/V materials and band engineering for hetero-tunnel junctions. The latter is seen as an ideal route towards achieving high drive currents and steep sub-threshold slopes at low supply voltages. This thesis investigates both Si Tunnel FETs and the route towards heterostructure Tunnel FETs, but also the technological challenges to achieve these device structures. The first part of this work deals with vapor-liquid-solid grown silicon in-situ doped n+-i-p nanowire Tunnel FETs in a lateral geometry, where the influence of the gate dielectric, i.e., SiO2 or HfO2, on device performance is investigated along with the study of low-temperature behavior. The devices having the strongest gate coupling due to the high-κ gate oxide HfO2 are shown to exhibit the best device performance as compared with the SiO2 gate stack. A vertical process for Si FETs is developed and improved to obtain a fully wrap-gate geometry. It is adaptable to different material systems and is the basis for the ongoing work on InAs-on-Si nanowire Tunnel FETs. Improved performance for these heterostructure devices requires in particular high doping concentrations as well as abrupt doping profiles to achieve high tunnel currents. Therefore, the second part focuses on the InAs material system and specifically the study of dopant incorporation. Doping is done in-situ using different precursors during growth. The InAs nanowires are grown in SiO2 mask openings on 〈111〉 Si substrates in a metal-organic vapor phase epitaxy process. The effect of the dopants and growth parameters on radial and vertical growth rates, wire morphology and resistivity is investigated. A method utilizing the measured Seebeck coefficient of the InAs nanowires to extract doping densities without the need of assuming a mobility value is presented. Two other reference methods where I-V characteristics of homo-and heterojunction InAs tunnel diodes are fitted by TCAD simulations confirm this approach. Doping densities ranging from 1·1017 cm−3 to 7.1·1019 cm−3 were achieved which is comparable to the highest doping concentration reported in bulk InAs. Furthermore, single vertical pn+-junctions are fabricated by growing n-type InAs nanowires on p-type InAs substrates, which show high tunnel current densities of 500 kA/cm2 at 0.3 V reverse bias. In the forward direction, negative differential resistance is obtained below 200 K, which is the characteristic feature of an Esaki diode.

EPFL2012

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CJM: A Compact Model for Double-Gate Junction FETs

Matthias Bucher, Farzan Jazaeri, Jean-Michel Sallese

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Furthermore, co-integration of JFET with CMOS technology is attractive. Physicsbased compact models for JFETs are however scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, transconductances and transcapacitances of symmetric DG JFETs, covering all regions of device operation, continuously from subthreshold to linear and saturation operation. This charge-based JFET model (called CJM) constitutes the basis of a full compact model of the DG JFET for analog, RF, and digital circuit simulation.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

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Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

Matthias Bucher, Farzan Jazaeri, Jean-Michel Sallese

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

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EPFL2012