Traitement analogique du signal

Résumé

Le traitement analogique du signal est un type de traitement du signal effectué sur des signaux analogiques continus par un processus analogique, par opposition au traitement numérique du signal discret où le traitement du signal est effectué par un processus numérique. Le terme analogique indique qu'on représente mathématiquement le signal comme une série de valeurs continues, contrairement au terme numérique, qui indique plutôt qu'on représente le signal par une série de valeurs discrètes. Les valeurs analogiques correspondent généralement à une tension, un courant électrique ou une charge électrique autour des composantes des appareils électroniques. Une erreur ou un bruit affectant ces quantités entraînera une erreur correspondante dans les signaux représentés par ces quantités. Parmi les exemples de traitement analogique du signal, on trouve les filtres répartiteurs dans les haut-parleurs, les commandes de volume, de graves et d'aigus sur les chaînes stéréo et les commandes de

Source officielle

https://fr.wikipedia.org/wiki/Traitement_analogique_du_signal

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Cours associés (20)

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Séances de cours associées (21)

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Chargement

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

Nowadays digital signal processing systems used for radar applications, communication systems or RF measurement equipments, require very high sample-rates. Sometimes these sample-rates are beyond the possibilities offered by conventional ADCs. To overcome these limits parallel architectures have been developed. The most commonly used it the one called "time-interleaved" conversion. This technique allows to achieve very-high sample-rates with circuits working at a lower frequency. The accuracy of "time-interleaved" systems is sensitive to sample-time errors. Some calibration techniques have been developed to reduce this sensitivity. They involve very sophisticated digital signal processing and, in most of the cases, they are not directly implemented on silicon but applied on measurement results in software. The goal of this thesis is to study the feasibility of a new parallel architecture for analog-to-digital conversion. This architecture must present a higher robustness to sample-time errors. The first part of this work is dedicated to time-interleaved converter. An analysis of their sensitivity to several imperfections, such as mismatches and systematic and random sample-time error is presented. This analysis is followed by a description of time-interleaved converter evolution, since the first implemented prototype to the current state of the art of the domain. The second part of this thesis focuses on the development of the new conversion technique called "frequency-interleaved". Two different approaches are studied: the first one is based on a Fourier series decomposition of the signal to convert and the second one is based on a Walsh series decomposition. During this study, theoretical and practical aspects are faced the one with the other, to combine signal processing and microelectronics together. It appears that the Fourier series approach offers modest performances and presents serious problems of implementation. Based on this study, the design of functional blocks of a Walsh series based system is proposed.

EPFL2009

Chargement

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

Chargement

The assumptions of linearity and autonomy assumed in circuit theory are known to be respected only partially by electroacoustic transducers. In particular, the dynamics range of the latter is limited by the audible nonlinear effects that they are causing. In the domain of active noise control, the distortion products limit noise reduction performance. The present thesis work stems from characterization of these observations. We want to design a real-time system compensating the nonlinearities of electroacoustic devices. The first part of this report concerns the nonlinearity effects. It is shown that the use of classical characterization methods of an electroacoustic device (harmonic distortion, intermodulation, frequency difference ...) is limited. Hence, they can not be used to determine the nonlinearity laws themselves, but rather only their effects for arbitrary excitations. First, a method based on multitone harmonic excitations has been proposed and validated. It has been applied for the characterization of loudspeaker prototypes using several different technologies, which are used for active noise reduction in an aircraft turboreactor. The second part of this work addresses the elaboration and validation of a nonlinearity effect compensation method. This method is based on the description of the nonlinearities by the Volterra series. For this, we need to place an upstream system, characterized by the inverse nonlinearity law of the loudspeaker system. After having determined precisely the Volterra kernels of the system to be characterized, the kernels of the upstream compensation system are determined by assuming that their cascade obeys to a linear law. For this purpose, a kernel measurement method in the frequency domain has been developed, validated and tested. Since we are concerned with loudspeakers, we took their flying time into account. The compensation method has been validated by computing the simulated response of the compensation circuit. Resulting analog signals have then been applied to the loudspeaker. Measured performances fulfill the expectations. In the last part, the compensation method has been applied in a real-time Digital Signal Processing) DSP controller, which allowed to realize a demonstrator to the implemented for future industrial applications.

EPFL2005

Chargement

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

EPFL2007

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

EPFL2009

EPFL2005