Publications associées à Non uniform memory access

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

The performance of programs written in languages following the dataflow model of computation (MoC) largely depends on the configuration (partitioning, mapping, scheduling, buffer dimensioning) chosen during the synthesis stages. Furthermore, this programmi ...

2022

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Andreas Peter Burg, Reza Ghanaatian Jahromi

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomi ...

2022

Rethinking Software Runtimes for Disaggregated Memory

Sanidhya Kashyap, Ivan Puddu

Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual mem ...

ASSOC COMPUTING MACHINERY2021

NrOS: Effective Replication and Sharing in an Operating System

Sanidhya Kashyap, Ankit Bhardwaj

Writing a correct operating system kernel is notoriously hard. Kernel code requires manual memory management and type-unsafe code and must efficiently handle complex, asynchronous events. In addition, increasing CPU core counts further complicate kernel de ...

USENIX ASSOC2021

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon, Yasir Mahmood Qureshi

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

Access pattern based optimization of memory access

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include identifying an access pattern associated with a database operation. The access pattern may include data required to perform the database operation. One or mor ...

2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Mirjana Stojilovic, Philip Brisk, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

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Non uniform memory access

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Rethinking Software Runtimes for Disaggregated Memory

NrOS: Effective Replication and Sharing in an Operating System

Blade: An in-Cache Computing Architecture for Edge Devices

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Access pattern based optimization of memory access

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Graph Chatbot

Chattez avec Graph Search

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Rethinking Software Runtimes for Disaggregated Memory

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Blade: An in-Cache Computing Architecture for Edge Devices

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

NrOS: Effective Replication and Sharing in an Operating System

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Access pattern based optimization of memory access