Samsung Electronics | EPFL Graph Search

Samsung Electronics (삼성전자) est une entreprise spécialisée dans la fabrication de produits électroniques. C'est une filiale à 100 % du Groupe Samsung, l'un des principaux chaebols coréens. En 2019, elle emploie et est la plus importante société dans le monde d'après le classement Forbes Global 2000. En 2017, son chiffre d'affaires s'est élevé à de dollars, ce qui la classe mondial de l'industrie du high-tech derrière Apple mais, devant des groupes comme IBM, Microsoft. Samsung a longtemps été un fabricant majeur de composants électroniques tels que des batteries lithium-ion, semi-conducteurs, circuits intégrés, mémoire flash et disques durs pour des clients tels que Apple, Sony, HTC et Nokia. Ces dernières années, l'entreprise s'est diversifiée dans le domaine de l'électronique grand public. C'est aujourd'hui le premier vendeur de téléphones mobiles et smartphones, notamment grâce à la popularité de ses modèles Samsung Galaxy. L'entreprise est également premier vendeur de tablette

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Marcos Vinícius Silva Oliveira

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These two requirements introduce new challenges, such as higher bandwidth and higher integration, in terms of data transfer and processing of trigger systems. Both problems have to be addressed, ensuring that hardware and firmware have low and fixed latency, and are reliable. Low latency is essential due to the limited storage available in the detector front-end pipelined memories. Fixed latency is needed because the trigger processing is pipelined, and the inputs need to be time-aligned at every processing step. Reliability is important for high trigger efficiency. If the trigger is not reliable, rare events can be discarded, and uninteresting events accepted. This Ph.D. thesis presents the upgrade of part of the trigger system of ATLAS (A Toroidal LHC AparatuS). ATLAS is one of the detectors at the world's largest and most powerful particle collider, the LHC (Large Hadron Collider) at CERN (European Center of Nuclear Research). The online trigger system of ATLAS is segmented in two levels. The first level is implemented with custom electronics. For the parts of the first level trigger not exposed to radiation, digital processing is primarily implemented using FPGA (Field Programmable Gate Array) devices. FPGAs offer high processing capacity with low-latency and re-programmability, i.e., the capability of changing the implemented logic. The second level is built from commercial computers, network switches, and custom software. The rate of bunch of particles crossing in the interaction point is 40 MHz, and the first level (Level-1) trigger needs to reduce the rate down to 100 kHz with a very low latency of 2.5 us. Part of the Level-1 trigger system, the MUCTPI (Muon to Central Trigger Processor Interface) connects the output of the barrel and endcap muon trigger to the CTP (Central Trigger Processor), which takes the final Level-1 accept decision. The first part of this Ph.D. thesis addresses the work on the data transfer part of the MUCTPI. Latency optimized FPGA (Field Programmable Gate Array) MGT (Multi-Gigabit Transceiver) configurations have been found. Moreover, an IP (Intellectual Property) core to synchronize data from 208 SL inputs with low and fixed latency has been developed. The total data transfer and synchronization latency is below 125 ns, corresponding to 60% of the latency budget. All MUCTPI on-board and off-board high-speed serial links have been tested. The Bit Error Rate (BER) values for all links running at 12.8 Gb/s have been measured as lower than one bit error per day with a confidence level of 95%. This value is acceptable as it corresponds to only one potential fake trigger or lost event per day. The second part of this thesis covers the development of the MUCTPI sorting network and its FPGA implementation using RTL (Register-Transfer Level) and HLS (High-Level Synthesis) approaches. Both approaches achieved a very low latency value of 31.25 ns, corresponding to only 15% of the latency budget. HLS provided advantages such as requiring much less design effort, enabling early testing, and having slightly higher performance in terms of timing slack and logic resource usage.

EPFL2021

System Design and Advanced Circuit Techniques for Bi-Directional Brain-Machine Interfaces

Wen-Yang Hsu

Bi-directional brain-machine interfaces (BBMIs) that can capture electrophysiological signals and provide feedback through electrical stimulation are emerging tools with various applica-tions in fundamental neuroscience research as well as in clinical treatments of neurological dis-orders. The strict requirements originating from the specific and vast application range of these systems pose severe constraints to the development of portable or implantable microelectronic devices in terms of safety and reliability, autonomy, critical physical dimensions. The power consumption of BBMI systems should be minimized to comply with safety require-ments and enable long-term operations in an energy-constraint environment. In addition, specific physical dimensions and the interconnect reduction are crucial to fully exploit novel MEMS technologies to forge BBMIs aiming at different applications. Both bottom-up and top-down improvements are mandatory contributors of innovations on critical circuit blocks and system-level optimization, respectively. The first part of this thesis presents a BBMI targeting for a specific clinical application, namely, deep brain stimulation which has been proven to effectively alleviate neurological disorders such as essential tremor and Parkinsonâs disease. A novel MEMS technology which encom-passes a 3-dimensional brain region is employed to enhance the localization of the stimulation site. In order to fully exploit this technology, system requirements such as the strict device di-mension, highly-limited inter-connects and simultaneous recordings from 5 channels at low-power consumption pose several challenges on the custom electronics. Using a single supply voltage, an application-specific integrated circuit (ASIC) shaped into a specific aspect ratio is presented to tackle the aforementioned challenges. While the presented work is suitable for open-loop operations which demand frequent post-surgery programming for optimized therapeutic effects, closed-loop approaches directly re-sponding to the recorded signals offers better patient experience. Such autonomous BBMIs require long-term operation in an energy-constrained environment as well as intensive compu-tations on data processing. Innovations on critical blocks such as recording front-ends and stimulators are thus highly desirable to achieve an aggressive power reduction. A novel high-frequency, switched-capacitor (HFSC) stimulation and active charge balancing scheme is proposed. It achieves a high energy efficiency and well-controlled stimulation charge in the presence of large electrode impedance variations. Furthermore, the HFSC can be imple-mented in a compact size without any external component to simultaneously enable multi-channel stimulation by deploying multiple stimulators. The proposed design shows significant benefits over the constant-current and voltage-mode stimulation methods. Finally, a time-based and digitally-intensive recording front-end is presented, which employs the pulse-width modulation (PWM) to generate a timing-encoded binary output. The proposed design achieves low-power operation using a highly scaled technology with a sin-gle 0.5V supply voltage, favorable for system integration in energy-constraint BBMI applications.

EPFL2018

Design, development, and validation of an in-situ biosensor array for metabolite monitoring of cell cultures

Cristina Boero, Sandro Carrara, Maria Antonietta Casulli, Giovanni De Micheli, Lorenzo Foglia, Marco Mazza, Jacopo Olivo

Conventional pharmaceutical processes involving cell culture growth are generally taken under control with expensive and long laboratory tests performed by direct sampling to evaluate quality. This traditional and well-established approach is just partially adequate in providing information about cell state. Electrochemical enzyme-based biosensors offer several advantages towards this application. In particular, they lend themselves to miniaturization and integration with cheap electronics. In the present work we go through the design, the development, and the validation of a self-contained device for the on-line measurement of metabolites in cell culture media. We microfabricated a sensing platform by using thin film technologies. We exploited electrodeposition to precisely immobilize carbon nano-tubes and enzymes on miniaturized working electrodes. We designed and realized the electronics to perform the electrochemical measurements and an Android application to display the measurements on smartphones and tablets. In cell culture media glucose biosensor shows a sensitivity of 4.7 ± 1.3 nA mM-1mm-2 and a detection limit of 1.4 mM (S/N=3σ), while for lactate biosensor the sensitivity is 12.2 ± 3.8 nA mM-1mm -2 and the detection limit is 0.3 mM. The whole system was then validated by monitoring U937 cell line over 88 h. Metabolic trends were fully congruent with cell density and viability. This self-contained device is a promising tool to provide more detailed information on cell metabolism that are unprecedented in cell biology.