Publications associées à Instruction set architecture

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

ACM2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

Ieee2016

Accelerating Machine Learning with Non-Volatile Memory: exploring device and circuit tradeoffs

Alessandro Fumarola, Severin Sidler

Large arrays of the same nonvolatile memories (NVM) being developed for Storage-Class Memory (SCM) such as Phase Change Memory (PCM) and Resistance RAM (ReRAM) - can also be used in non-Von Neumann neuromorphic computational schemes, with device conductanc ...

Ieee2016

Highly Scalable Digital Silicon Photonic MEMS Switches

Niels Quack

Optical circuit switches with fast switching times can provide rapidly reconfigurable bandwidth in data center networks. Silicon photonic switches are attractive candidates with their fast response times and CMOS process compatibility. In this paper, we re ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Exploiting Large Image Sets for Road Scene Parsing

Mathieu Salzmann

There is an increasing interest in exploiting multiple images for scene understanding, with great progress in areas such as cosegmentation and video segmentation. Jointly analyzing the images in a large set offers the opportunity to exploit a greater sourc ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Multi-Objective Parametric Query Optimization

Christoph Koch, Immanuel Trummer

We propose a generalization of the classical database query optimization problem: multi-objective parametric query optimization (MPQ). MPQ compares alternative processing plans according to multiple execution cost metrics. It also models missing pieces of ...

Association for Computing Machinery2016

Establishing a base of trust with performance counters for enterprise workloads

Willy Zwaenepoel, Andrzej Pawel Nowak

Understanding the performance of large, complex enterprise-class applications is an important, yet nontrivial task. Methods using hardware performance counters, such as profiling through event-based sampling, are often favored over instrumentation for anal ...

2015

Confluence: unified instruction supply for scale-out servers

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instruction-supply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching tec ...

ACM Press2015

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Instruction set architecture

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction

Accelerating Machine Learning with Non-Volatile Memory: exploring device and circuit tradeoffs

Highly Scalable Digital Silicon Photonic MEMS Switches

Exploiting Large Image Sets for Road Scene Parsing

Multi-Objective Parametric Query Optimization

Establishing a base of trust with performance counters for enterprise workloads

Confluence: unified instruction supply for scale-out servers

Graph Chatbot

Chattez avec Graph Search

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction

Highly Scalable Digital Silicon Photonic MEMS Switches

Accelerating Machine Learning with Non-Volatile Memory: exploring device and circuit tradeoffs

Confluence: unified instruction supply for scale-out servers

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Multi-Objective Parametric Query Optimization

Establishing a base of trust with performance counters for enterprise workloads

Exploiting Large Image Sets for Road Scene Parsing