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Concept

Symmetric multiprocessing

Un multiprocesseur symétrique (à mémoire partagée), ou symmetric shared memory multiprocessor (SMP), est une architecture parallèle qui consiste à multiplier les processeurs identiques au sein d'un ordinateur, de manière à augmenter la puissance de calcul, tout en conservant une unique mémoire. Disposer de plusieurs processeurs permet d'exécuter simultanément plusieurs processus du système, utilisateur ou noyau en leur allouant l'un ou l'autre des processeurs disponibles, ce qui augmente la fluidité lors de l'exécution de plusieurs programmes, et permet à un processus d'utiliser plus de ressources de calcul en créant plusieurs threads. Ce principe crée néanmoins un goulot d'étranglement au niveau de la mémoire principale, qui est partagée par tous les processeurs. C'est pour cette raison que des systèmes à mémoire répartie partagée et à mémoire distribuée sont apparus. Voir aussi

Multiprocesseur
Asymmetric multiprocessing

Catégorie:Architecture informatique

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Séances de cours associées (8)

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Système d'exploitation

En informatique, un système d'exploitation (souvent appelé OS — de l'anglais operating system — ou parfois SE — en français) est un ensemble de programmes qui dirige l'utilisation des ressources d'u

Central processing unit

A central processing unit (CPU)—also called a central processor or main processor—is the most important processor in a given computer. Its electronic circuitry executes instructions of a computer pr

Multitâche

Un système d'exploitation est multitâche () s’il permet d’exécuter, de façon apparemment simultanée, plusieurs programmes informatiques. On parle également de multiprogrammation. Cette fonction est

CS-307: Introduction to multiprocessor architecture

Multiprocessors are a core component in all types of computing infrastructure, from phones to datacenters. This course will build on the prerequisites of processor design and concurrency to introduce the essential technologies required to combine multiple processing elements into a single computer.

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Ce cours présente une introduction à la théorie et aux méthodes d'analyse et de résolution des circuits électriques.

EE-405: Fundamentals of electrical circuits and systems

This course provides an overview of fundamental concepts of signal processing and electric circuits.

Evaluating scheduling policies for fine-grain communication protocols on a cluster of SMPs

Babak Falsafi, David Wood

Distributed-memory parallel computers and networks of workstations (NOWs) both rely on efficient communication over increasingly high-speed networks. Software communication protocols are often the performance bottleneck. Several current and proposed parallel systems address this problem by dedicating one general-purpose processor in a symmetric multiprocessor (SMP) node specifically for protocol processing. This protocol processing convention reduces communication latency and increases effective bandwidth, but also reduces the peak performance since the dedicated processor no longer performs computation. In this paper, we study a parallel machine with SMP nodes and compare two protocol processing policies: the Fixed policy, which uses a dedicated protocol processor; and the Floating policy, where all processors perform both computation and protocol processing. The results from synthetic microbenchmarks and five macrobenchmarks show that: (i) a dedicated protocol processor benefits light-weight protocols much more than heavy-weight protocols, (ii) a dedicated protocol processor is generally advantageous when there are four or more processors per node, (iii) multiprocessor node performance is not as sensitive to interrupt overhead as uniprocessor node because a message arrival is likely to find an idle processor on a multiprocessor node, thereby eliminating interrupts, (iv) the system with the lowest cost-performance will include a dedicated protocol processor when interrupt overheads are much higher than protocol weight - as in light-weight protocols. © 2005 Elsevier Inc. All rights reserved.

2005

Chargement

Scheduling communication on an SMP node parallel machine

Babak Falsafi, David Wood

Distributed-memory parallel computers and networks of workstations (NOWs) both rely on efficient communication over increasingly high-speed networks. Software communication protocols are often the performance bottleneck. Several current and proposed parallel systems address this problem by dedicating one general-purpose processor in a symmetric multiprocessor (SMP) node specifically for protocol processing. This scheduling convention reduces communication latency and increases effective bandwidth but also reduces the peak performance since the dedicated processor no longer performs computation. In this paper, we study a parallel machine with SMP nodes and compare two protocol processing policies: Fixed, which uses a dedicated protocol processor; and Floating, where all processors perform both computation and protocol processing. The results from synthetic microbenchmarks and five macrobenchmarks show that: (i) a dedicated protocol processor benefits light-weight protocols much more than heavy- weight protocols; (ii) fixed improves performance over Floating when communication becomes the bottleneck, which is more likely when the application is very communication-intensive, overheads are very high, or there are multiple (i.e., more than two) processors per node; (iii) a system with optimal cost-effectiveness is likely to include a dedicated protocol processor, at least for light-weight protocols

1997

Chargement

Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator

Babak Falsafi, James Richard Larus, David Wood

To analyze new, parallel computers, developers must rapidly simulate designs running realistic workloads. Historically, direct execution and a parallel host have accelerated simulations, although these techniques have typically lacked portability. Through four key operations, the Wisconsin Wind Tunnel II can easily run simulations on Sparc platforms ranging from a workstation cluster to a symmetric multiprocessor.

2000

Chargement