Concept

Cache control instruction

Publications associées (81)

High-Performance Communication Primitives and Data Structures on Message-Passing Manycores

The constant increase in single core frequency reached a plateau during recent years since the produced heat inside the chip cannot be cooled down by existing technologies anymore. An alternative to harvest more computational power per die is to fabricate ...

EPFL2014

ALLARM: Optimizing Sparse Directories for Thread-Local Data

Amitabha Roy

Large-scale cache-coherent systems often impose unnecessary overhead on data that is thread-private for the whole of its lifetime. These include resources devoted to tracking the coherence state of the data, as well as unnecessary coherence messages sent o ...

2014

Network-on-chip using request and reply trees for low-latency processor-memory communication

Babak Falsafi, Boris Robert Grot

A Network-On-Chip (NOC) organization comprises a die having a cache area and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, whereby the at least one cac ...

2014

Multi-Grain Coherence Directory

Babak Falsafi

Conventional directory coherence operates at the finest granularity possible, that of a cache block. While simple, this organization fails to exploit frequent application behavior: at any given point in time, large, continuous chunks of memory are often ac ...

2013

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks

Paolo Ienne, Ali Galip Bayrak, Wayne Burleson, Nikola Velickovic

Embedded cryptographic systems, such as smart cards, require secure implementations that are robust to a variety of low-level attacks. Side-Channel Attacks (SCA) exploit the information such as power consumption, electromagnetic radiation and acoustic leak ...

2012

Scale-Out Processors

Babak Falsafi, Michael Ferdman, Boris Robert Grot, Yusuf Onur Koçberber, Pejman Lotfi Kamran, Stavros Volos, Javier Picorel Obando, Al Mutaz Adileh

Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by ...

Ieee2012

Spatiotemporal Coherence Tracking

Mohammad Alisafaee

Chip-multiprocessors require a coherence directory to track data sharing and order accesses to the shared data. Scaling coherence directories to support a large number of cores is challenging due to excessive area requirements of the directories. The state ...

2012

NOC-Out: Microarchitecting a Scale-Out Processor

Babak Falsafi, Boris Robert Grot, Pejman Lotfi Kamran

Scale-out server workloads benefit from many-core processor organizations that enable high throughput thanks to abundant request-level parallelism. A key characteristic of these workloads is the large instruction footprint that exceeds the capacity of priv ...

2012

A Data-oriented Transaction Execution Engine and Supporting Tools

Anastasia Ailamaki, Miguel Sérgio De Oliveira Branco, Frederick Ryan Johnson, Pinar Tözün, Ippokratis Pandis, Danica Porobic, Dimitrios Karampinas

Conventional OLTP systems assign each transaction to a worker thread and that thread accesses data, depending on what the transaction dictates. This thread-to-transaction work assignment policy leads to unpredictable accesses. The unpredictability forces e ...

2011

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