Concept

Cache control instruction

Publications associées (81)

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An integrated hardware/software approach for run-time scratch-management

David Atienza Alonso, Luca Benini

An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applications on the architecture. However, today’s embedded operating systems abstrac ...

ACM/IEEE Press2004

Hiding Synchronization Delays in a GALS Processor Microarchitecture

Sandhya Dwarkadas

We analyze an Alpha 21264-like Globally–Asynchronous, Locally–Synchronous (GALS) processor organized as a Multiple Clock Domain (MCD) microarchitecture and identify the architectural features of the processor that influence the limited performance degradat ...

2004

Miss Rate Prediction across All Program Inputs

Chen Ding

Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets. This paper uses our recently published ...

2003

Near-optimal precharging in high-performance nanoscale CMOS caches

Babak Falsafi

High-performance caches statically pull up the bit-lines in all cache subarrays to optimize cache access latency. Unfortunately, such architecture results in a significant waste of energy in nanoscale CMOS implementations due to high leakage and bitline di ...

2003

Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay

Babak Falsafi

Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in t ...

2002

Joint Server Scheduling and Proxy Caching for Video Delivery

Pascal Frossard

We consider the delivery of video assets over a best-effort network, possibly through a caching proxy located close to the clients generating the requests. We are interested in the joint server scheduling and prefix/partial caching strategy that minimizes ...

2002

Two approaches for applet-based visible human slice extraction

Roger Hersch, Sebastian Gerlach

Real-time interactive slicing is a tool of choice for exploring 3D anatomic data sets such as the Visible Human. We offer real-time slicing on the Web by partitioning the application between a Java applet (the client) and the Web server. Two approaches for ...

SPIE-Int. Soc. Opt. Eng2001

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Babak Falsafi

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately, reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold ...

2001

Reducing leakage in a high-performance deep-submicron instruction cache

Babak Falsafi

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold ...

2001

Dead-block prediction & dead-block correlating prefetchers

Babak Falsafi

Effective data prefetching requires accurate mechanisms to predict both “which” cache blocks to prefetch and “when” to prefetch them. This paper proposes the Dead-Block Predictors (DBPs), trace-based predictors that accurately identify “when” an Ll data ca ...

2001