Publications associées à BiCMOS

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Mihai Adrian Ionescu, Christian Enz, Igor Stolichnov, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

2019

Towards Oxide Electronics: a Roadmap

Ulf Anders Hagfeldt, Francisco Sanchez, Mauro Fanciulli, Monica Marcela Lira Cantu, Brahim Dkhil

At the end of a rush lasting over half a century, in which CMOS technology has been experiencing a constant and breathtaking increase of device speed and density, Moore's law is approaching the insurmountable barrier given by the ultimate atomic nature of ...

2019

Influence of Halo Implantations on the Total Ionizing Dose Response of 28-nm pMOSFETs Irradiated to Ultrahigh Doses

Christian Enz

In this paper, the total ionizing dose (TID) response of a commercial 28-nm high-k CMOS technology at ultrahigh doses is measured and discussed. The degradation of pMOSFETs depends not only on the channel width but also on the channel length. Short-channel ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

CJM: A Compact Model for Double-Gate Junction FETs

Jean-Michel Sallese, Farzan Jazaeri, Matthias Bucher

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-n ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

Maher Kayal, Mathieu Yves Hervé Coustans, Thomas Eberhardt, Laurent Fesquet

This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in ...

IEEE2018

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

Amongst 2-dimensional (2D) semiconductors of the transition-metal di-chalcogenide (TMDC) family [1], tungsten diselenide (WSe2) has shown ambipolar behavior [2], [3] coupled with high carrier mobility [4] and CMOS-like devices have been experimentally demo ...

IEEE2018

A Sub-mu W/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing

Alexandre Schmid, Reza Ranjandish

An accurate 16-channel seizure detection system-on-chip is presented, which is based on extracting features from the compressed recorded data using multichannel compressive sensing (MCS). MCS is used to reduce the transmission data rate of sparse biologica ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Jean-Michel Sallese, Christophe Lallement

Transconductance efficiency (g(m)/I-D) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of g(m)/I-D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully deple ...

2018

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BiCMOS

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Towards Oxide Electronics: a Roadmap

Influence of Halo Implantations on the Total Ionizing Dose Response of 28-nm pMOSFETs Irradiated to Ultrahigh Doses

CJM: A Compact Model for Double-Gate Junction FETs

Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors

A Sub-mu W/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing

Integrated Bio/Nano/CMOS Interfaces for Electrochemical Molecular Sensing

Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference

Graph Chatbot

Chattez avec Graph Search

Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

A Sub-mu W/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing

Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Influence of Halo Implantations on the Total Ionizing Dose Response of 28-nm pMOSFETs Irradiated to Ultrahigh Doses

Integrated Bio/Nano/CMOS Interfaces for Electrochemical Molecular Sensing

Towards Oxide Electronics: a Roadmap

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors

CJM: A Compact Model for Double-Gate Junction FETs

A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference