Concept

Altera

Publications associées (102)

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Paolo Ienne, Grace Zgheib, Stefan Nikolic

The idea of introducing dedicated, fast paths between certain FPGA elements in order to reduce delay is neither new nor particularly hard to come up with. What is less obvious, however, is how to put such paths to actual use. In this work, we propose an ef ...

IEEE2020

Design and experimental validation of an FPGA-based PMU simultaneously compliant with P and M performance classes

Mario Paolone, Asja Derviskadic

Low-inertia grids are characterized by high shares of harmonic and inter-harmonic distortion, produced by the inverters that interface non-conventional generation assets to the electrical grid. These interfering tones largely compromise synchrophasor estim ...

2020

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

Francesco Regazzoni, Mirjana Stojilovic, Louis Coulon, Ognjen Glamocanin

Recent works have demonstrated the possibility of extracting secrets from a cryptographic core running on an FPGA by means of remote power analysis attacks. To mount these attacks, an adversary implements a voltage fluctuation sensor in the FPGA logic, rec ...

2020

Exact Synthesis of Boolean Functions in Majority-of-five Forms

Giovanni De Micheli, Mathias Soeken, Winston Jason Haaswijk, Zhufei Chu

Recent studies show that majority-based logic synthesis is beneficial for both traditional and nanotechnology digital designs. However, most of the existing synthesis algorithms for majority logic generate majority-of-three (M-3) networks. The optimization ...

IEEE2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

Quantum computers enable a massive speed-up in calculations, thanks to the nature of quantum operations. To unlock quantum computation, a classical system infrastructure is required for the control of qubits and processing of their data. While qubits are g ...

2018

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Mirjana Stojilovic, Philip Brisk

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

Majority Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa, Odysseas Zografos

The majority function (xyz) evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority f ...

ASSOC COMPUTING MACHINERY2018

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The oppo ...

2018

Spatial: A Language and Compiler for Application Accelerators

Christos Kozyrakis, Yunqi Zhang

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for pr ...

ASSOC COMPUTING MACHINERY2018

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