Concept

Very long instruction word

Publications associées (100)

Experimental Study and Numerical Simulation of the Flindt Draft Tube Rotating Vortex

The dynamics of the rotating vortex taking place in the discharge ring of a Francis turbine for partial flow rate operating conditions and cavitation free conditions is studied by carrying out both experimental flow survey and numerical simulations. 2D las ...

2007

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007

Compilation for Delay Impact Minimization in VLIW Embedded Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow’s embedded devices need to run high resolution multimedia as well as need to support multistandard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In thi ...

IEEE Press2006

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006

Exploiting reference idempotency to reduce speculative storage overflow

Babak Falsafi

Recent proposals for multithreaded architectures employ speculative execution to allow threads with unknown dependences to execute speculatively in parallel. The architectures use hardware speculative storage to buffer speculative data, track data dependen ...

2006

Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs

David Atienza Alonso, José Luis Ayala Rodrigo, Roman Hermida Correa

In this paper we introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This work includes a set of architectural extensions and special loop unrolling te ...

IEEE Press2005

Understanding the performance of concurrent error detecting superscalar microarchitectures

Babak Falsafi

Superscalar out-of-order microarchitectures can be modified to support redundant execution of a program as two concurrent threads for soft-error detection. However, the extra workload from redundant execution incurs a performance penalty due to increased c ...

2005

ReCast: Boosting tag line buffer coverage in low-power high-level caches "for free"

Babak Falsafi

We revisit the idea of using small line buffers in-front of caches. We propose ReCast, a tiny tag set cache that filters a significant number of tag probes to the L2 tag array thus reducing power. The key contribution in ReCast is S-Shift, a simple indexin ...

2005

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in partic ...

EPFL2004

Efficient resource sharing in concurrent error detecting superscalar microarchitectures

Babak Falsafi

Previous proposals for soft-error tolerance have called for redundantly executing a program as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar design, the extra workload from redundant execution induces a severe perform ...

2004

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