Ordinateur de bureau | EPFL Graph Search

Un ordinateur de bureau ou ordinateur fixe (desktop computer en anglais) est un ordinateur personnel destiné à être utilisé sur un bureau ou tout autre endroit fixe à cause de ses dimensions, de sa masse et de son alimentation électrique. L'unité centrale est le plus souvent composé d'un boîtier qui comprend un bloc d'alimentation, une carte-mère (circuit imprimé sur lequel est fixé un micro-processeur en tant qu'unité centrale de traitement, la mémoire de traitement, les bus informatiques et d'autres composants électroniques) ainsi qu'un système d'entrées/sorties. Ce boîtier peut être connecté en permanence à plusieurs périphériques comme un écran, un clavier, une souris, des haut-parleurs, un micro, un disque dur externe, une imprimante, un scanneur Le boîtier peut être placé à la verticale ou l'horizontale, sur le bureau, à côté ou sous celui-ci. Histoire Origines Avant la démocratisation des microprocesseurs, la rumeur voulait qu'un ordinateur qui tiendrait

Improving the boneh-franklin traitor tracing scheme

Pascal Junod, Alexandre Karlov, Arjen Lenstra

Traitor tracing schemes are cryptographically secure broadcast methods that allow identification of conspirators: if a pirate key is generated by k traitors out of a static set of l legitimate users, then all traitors can be identified given the pirate key. In this paper we address three practicality and security issues of the Boneh-Franklin traitor- tracing scheme. In the first place, without changing the original scheme, we modify its tracing procedure in the non-black-box model such that it allows identification of k traitors in time O˜(k2), as opposed to the original tracing complexity O˜(l). This new tracing procedure works independently of the nature of the Reed-Solomon code used to watermark private keys. As a consequence, in applications with billions of users it takes just a few minutes on a common desktop computer to identify large collusions. Secondly, we exhibit the lack of practical value of list- decoding algorithms to identify more than k traitors. Finally, we show that 2k traitors can derive the keys of all legitimate users and we propose afixtothis security issue. © International Association for Cryptologic Research 2009.

Springer Verlag2009

Designable Visual Markers

Enrico Costanza, Jeffrey Huang

Visual markers are graphic symbols designed to be easily recognised by machines. They are traditionally used to,track goods, but there is increasing interest in their application to mobile HCI. By scanning a visual marker through a camera phone, users can retrieve localised information and access mobile services. One missed opportunity in current visual marker systems is that the markers themselves cannot be visually designed; they are not expressive to humans, and thus fail to convey information before being scanned. This paper provides an overview of d-touch, an open source system that allows users to create their own markers, and control their aesthetic qualities. The system runs in real-time on mobile phones and desktop computers. To increase computational efficiency, d-touch imposes constraints on the design of the markers in terms of the relationship of dark and light regions in the symbols. We report a user study in which pairs of novice users generated between 3 and 27 valid and expressive markers within one hour of being introduced to the system, demonstrating its flexibility and ease of use.

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2009

An FPGA-based syntactic parser for large size real-life context-free grammars

Cristian Raul Ciressan

This thesis is at the crossroad between Natural Language Processing (NLP) and digital circuit design. It aims at delivering a custom hardware coprocessor for accelerating natural language parsing. The coprocessor has to parse real-life natural language and is targeted to be useful in several NLP applications that are time constrained or need to process large amounts of data. More precisely, the three goals of this thesis are: (1) to propose an efficient FPGA-based coprocessor for natural language syntactic analysis that can deal with inputs in the form of word lattices, (2) to implement the coprocessor in a hardware tool ready for integration within an ordinary desktop computer and (3) to offer an interface (i.e. software library) between the hardware tool and a potential natural language software application, running on the desktop computer. The Field Programmable Gate Array (FPGA) technology has been chosen as the core of the coprocessor implementation due to its ability to efficiently exploit all levels of parallelism available in the implemented algorithms in a cost-effective solution. In addition, the FPGA technology makes it possible to efficiently design and test such a hardware coprocessor. A final reason is that the future general-purpose processors are expected to contain reconfigurable resources. In such a context, an IP core implementing an efficient context-free parser ready to be configured within the reconfigurable resources of the general-purpose processor would be a support for any application relying on context-free parsing and running on that general-purpose processor. The context-free grammar parsing algorithms that have been implemented are the standard CYK algorithm and an enhanced version of the CYK algorithm developed at the EPFL Artificial Intelligence Laboratory. These algorithms were selected (1) due to their intrinsic properties of regular data flow and data processing that make them well suited for a hardware implementation, (2) for their property of producing partial parse trees which makes them adapted for further shallow parsing and (3) for being able to parse word lattices.

EPFL2002

An FPGA-based syntactic parser for large size real-life context-free grammars

Cristian Raul Ciressan

EPFL2002