Publications associées à Contrôleur mémoire

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

David Atienza Alonso, Giovanni Ansaloni, José Angel Miranda Calero, Rubén Rodríguez Álvarez, Juan Pablo Sapriza Araujo, Benoît Walter Denkinger

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

2024

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Zhenyu Wang, Asmund Kjellegaard Ottesen, Yanfei Zhao, Guilherme Migliato Marega, Hyungoo Ji

Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector ...

2023

Chaosity: Understanding Contemporary NUMA-architectures

Anastasia Ailamaki, Viktor Sanca, Hamish Mcniece Hill Nicholson, Andreea Nica, Syed Mohammad Aunn Raza

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

AstriFlash: A Flash-Based System for Online Services

Babak Falsafi, Lei Yan, Siddharth Gupta, Mark Johnathon Sutherland, Yunho Oh

Modern datacenters host datasets in DRAM to offer large-scale online services with tight tail-latency requirements. Unfortunately, as DRAM is expensive and increasingly difficult to scale, datacenter operators are forced to consider denser storage technolo ...

2022

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Andreas Peter Burg, Reza Ghanaatian Jahromi

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomi ...

2022

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

Andras Kis, Guilherme Migliato Marega

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatil ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

2022 roadmap on neuromorphic computing and engineering

Srikanth Ramaswamy, Carlo Ricciardi, Elisa Donati, Yihwa Kim, Silvia Tolu, Xuan Li, Abu Sebastian, Emre Neftci, Roberto Galeazzi

Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer i ...

IOP Publishing Ltd2022

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Alexandre Schmid, Lizeth Gonzalez Carabarin

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

IEEE2022

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Contrôleur mémoire

EdgeAI-Aware Design of In-Memory Computing Architectures

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

Chaosity: Understanding Contemporary NUMA-architectures

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

AstriFlash: A Flash-Based System for Online Services

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

2022 roadmap on neuromorphic computing and engineering

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Graph Chatbot

Chattez avec Graph Search

EdgeAI-Aware Design of In-Memory Computing Architectures

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

AstriFlash: A Flash-Based System for Online Services

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

Chaosity: Understanding Contemporary NUMA-architectures

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

2022 roadmap on neuromorphic computing and engineering

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations