Stack-Smashing Protector | EPFL Graph Search

Le Stack-Smashing Protector (également appelé SSP, et autrefois connu sous le nom de ProPolice) est une extension au compilateur GCC qui permet de minimiser les dommages qui peuvent être dus à des attaques de type dépassement de tampon. En particulier, il fournit une protection contre la corruption de pile (stack-smashing). La protection Stack-Smashing Protector a originairement été écrite, et est toujours entretenue, par Hiroaki Etoh d'IBM. La première implémentation a été faite pour GCC 3 et a ensuite été réécrite de façon moins intrusive puis intégrée dans GCC 4.1. Différentes options Il existe plusieurs options de compilation dans gcc pour activer les différentes protections contre les débordements de tampon :

-fstack-protector
-fstack-protector-all
-fstack-protector-strong (à partir de GCC 4.9)
-Wstack-protector

Notes et références Liens externes

Site officiel

Worst-case execution time analysis for many-core architectures with NoC

Alena Simalatsar, Stefanos Skalistis

The optimal deployment of data streaming applications onto multi-/many-core platform providing real-time guarantees requires to solve the application partitioning and placement, buffer allocation and task mapping and scheduling optimisation problem using the tasks Worst-Case Execution Time (WCET). In turn, tasks WCET varies due to interferences that tasks experience when accessing shared resources that depend on the solutions of the optimisation problem. In this paper we propose a detailed interference-based method that first over-approximates the WCET and then tightens it by pruning out the interferences from tasks not overlapping in time and memory. We prove that derived bounds are safe. We have found that interferences on average amount to 10% of WCET, and were able to improve latency guarantee up to 34%.

Springer Int Publishing Ag2016

Near-optimal Deployment of Dataflow Applications on Many-core Platforms with Real-time Guarantees

Alena Simalatsar, Stefanos Skalistis

Safe and optimal deployment of data-streaming applications on many-core platforms requires the realistic estimation of task Worst-Case Execution Time (WCET). On the other hand, task WCET depends on the deployment solution, due to the varying number of interferences on shared resources, thus introducing a cyclic dependency. Moreover, WCET is still an over-approximation of the Actual Execution Time (AET), thus leaving room for run-time optimisation. In this paper we introduce an offline/online optimisation approach. In the offline phase, we first break the cyclic dependency and acquire safe and near-optimal solutions for tasks partitioning/placement, mapping, scheduling and buffer allocation. Then, we tighten the WCETs and update the scheduling function accordingly. In the online phase we introduce a safe distributed readjustment of the offline schedule, based on the AET. Experiments on a Kalray MPPA-256 platform show a tightening of the guaranteed latency up to 46% in the offline phase, and 41% latency reduction in the online phase. In total, we achieve more than 50% of latency reduction.

IEEE2017

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed.

EPFL2015

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

EPFL2015