Publications associées à Horloge parlante

A Low Power Multi-Class Migraine Detection Processor Based on Somatosensory Evoked Potentials

Mahsa Shoaran, Bingzhao Zhu, Zain Taufique

Migraine is a disabling neurological disorder that can be recurrent and persist for long durations. The continuous monitoring of the brain activities can enable the patient to respond on time before the occurrence of the approaching migraine episode to min ...

2021

Rocker oscillator time bases

Simon Nessim Henein, Ilan Vardi

Since the invention of the pendulum clock by Christiaan Huygens in 1657, precision timekeepers have been regulated by oscillators. Although the pendulum is not an isochronous oscillator, its introduction as a time basis for clock regulation led to a signif ...

2021

Design of atomic clock cavity based on a loop-gap geometry and modified boundary conditions

Anja Skrivervik, Anton Evgeniev Ivanov

In this study, we investigate a concept that can be used to improve the magnetic field homogeneity in a microwave cavity applied in a novel, high-performance atomic frequency standard. We show that by modifying the boundary conditions in the case of a loop ...

2017

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

2017

Consistency Models in Distributed Systems with Physical Clocks

Jiaqing Du

Most existing distributed systems use logical clocks to order events in the implementation of various consistency models. Although logical clocks are straightforward to implement and maintain, they may affect the scalability, availability, and latency of t ...

EPFL2014

Modeling and Design Techniques for 3-D ICs under Process, Voltage, and Temperature Variations

Hu Xu

Three-dimensional (3-D) integration is a promising solution to further enhance the density and performance of modern integrated circuits (ICs). In 3-D ICs, multiple dies (tiers or planes) are vertically stacked. These dies can be designed and fabricated se ...

EPFL2012

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional ...

2012

Skew Variability in 3-D ICs with Multiple Clock Domains

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock di ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Clock Distribution Networks in 3-D Integrated Systems

Vasileios Pavlidis

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock di ...

2011

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Seyed Armin Tajalli, Yusuf Leblebici

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

2010