Output impedance

Résumé

The output impedance of an electrical network is the measure of the opposition to current flow (impedance), both static (resistance) and dynamic (reactance), into the load network being connected that is internal to the electrical source. The output impedance is a measure of the source's propensity to drop in voltage when the load draws current, the source network being the portion of the network that transmits and the load network being the portion of the network that consumes. Because of this the output impedance is sometimes referred to as the source impedance or internal impedance. Description All devices and connections have non-zero resistance and reactance, and therefore no device can be a perfect source. The output impedance is often used to model the source's response to current flow. Some portion of the device's measured output impedance may not physically exist within the device; some are artifacts that are due to the chemical, thermodynamic, or mechanical p

Source officielle

https://en.wikipedia.org/wiki/Output_impedance

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This course introduces the analysis and design of linear analog circuits based on operational amplifiers. A Laplace early approach is chosen to treat important concepts such as time and frequency responses, convolution, and filter design. The course is complemented with exercises and simulations.

L'étudiant maîtrise la conception et la mise en oeuvre des circuits et systèmes électroniques sous forme discrète et intégrée. L'accent est mis sur les applicationb dans le domaine des télécommunications.

Ce cours introduit les composants à semiconducteurs électroniques de base : diodes à jonction PN, transistors bipolaires et MOS. Leurs modes de fonctionnement en DC et AC sont étudiés. Les circuits élémentaires à base de transistors bipolaires sont présentés et analysés.

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A 49 mu W 6th-Order Chebyshev SSF-based Low-Pass Analog Filter for IEEE 802.11ax

Daniel Mathias Bold, Salvatore Collura, Christian Enz, Alessandro Pezzotta

In this paper a continuous-time low-pass analog filter based on the Cascoded Super Source Follower (C-SSF) architecture, implemented in a 28-nm bulk CMOS process, is presented. The target application is the transceiver analog baseband for the next-generation IEEE 802.11ax WiFi standard. To comply with the high-selectivity requirements, a 6th-order Chebyshev transfer function has been implemented as a cascade of three biquadratic cells. The high quality factors required by such topology have been achieved by cascoding the feedback transistor in the standard SSF cell, reducing the quality factor dependence on the output conductance of the source follower transistor. Designed with the Inversion-Coefficient (IC) methodology, the filter is able to operate for channel bandwidths ranging from 10 MHz to 20 MHz by changing its bias current. Measurement results show that the filter has a minimum noise power of -55.1 dBm and a maximum IIP3 of 14 dBm consuming 49 mu W, i.e. 8.17 mu W per pole, occupying an area of 0.0099 mm(2).

IEEE2020

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Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures

Arnout Lodewijk M Beckers, Christian Enz, Louis Hutin, Farzan Jazaeri

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

2018

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Influence of heart motion on cardiac output estimation by means of electrical impedance tomography: a case study

Fabian Braun, Mathieu Lemay, Martin Proença, Michaël Rapin, Jean-Philippe Thiran

Electrical impedance tomography (EIT) is a non-invasive imaging technique that can measure cardiac-related intra-thoracic impedance changes. EIT-based cardiac output estimation relies on the assumption that the amplitude of the impedance change in the ventricular region is representative of stroke volume (SV). However, other factors such as heart motion can significantly affect this ventricular impedance change. In the present case study, a magnetic resonance imaging-based dynamic bio-impedance model fitting the morphology of a single male subject was built. Simulations were performed to evaluate the contribution of heart motion and its influence on EIT-based SV estimation. Myocardial deformation was found to be the main contributor to the ventricular impedance change (56%). However, motion-induced impedance changes showed a strong correlation (r = 0.978) with left ventricular volume. We explained this by the quasi-incompressibility of blood and myocardium. As a result, EIT achieved excellent accuracy in estimating a wide range of simulated SV values (error distribution of 0.57 +/- 2.19 ml (1.02 +/- 2.62%) and correlation of r = 0.996 after a two-point calibration was applied to convert impedance values to millilitres). As the model was based on one single subject, the strong correlation found between motion-induced changes and ventricular volume remains to be verified in larger datasets.

Iop Publishing Ltd2015

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