Publications associées à Explicitly parallel instruction computing

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

IEEE2022

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

ASSOC COMPUTING MACHINERY2022

Real-Time Nonlinear Model Predictive Control for Fast Mechatronic Systems

Petr Listov

This thesis presents an efficient and extensible numerical software framework for real-time model-based control. We are motivated by complex and challenging mechatronic applications spanning from flight control of fixed-wing aircraft and thrust vector cont ...

EPFL2022

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Anatoly Prihozhy

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

SPRINGER2020

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e(x)

Felix Schürmann, Francesco Cremonesi, Timothée Ewart, Fabien Jonathan Delalondre

The evaluation of small degree polynomials is critical for the computation of elementary functions. It has been extensively studied and is well documented. In this article, we evaluate existing methods for polynomial evaluation on superscalar architecture. ...

2020

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon, Yasir Mahmood Qureshi

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

Microwave inductive proximity sensors with sub-pm/Hz1/2 resolution

Giovanni Boero, Nergiz Sahin Solmaz, Alessandro Valentino Matheoud, Lénaïc Frehner

Inductive proximity sensors are low-cost and versatile detectors achieving resolutions in the nm and sub-nm range. Their typical working frequency ranges from tens of kHz to a few MHz. Operation at higher frequencies is considered as a possible route for t ...

2019

A 32kHz crystal oscillator leveraging voltage scaling in an ultra-low power 40nA real-time clock

Maher Kayal, Luca Rossi, François Krummenacher, Mathieu Yves Hervé Coustans

In this paper, an ultra-low power consumption crystal oscillator embedded in an RTC module (ASIC and its crystal resonator) is presented. The technique leverages oscillation amplitude and loads capacitance scaling; it incorporates transistor level merging ...

IEEE2018

Exploiting Compute Caches for Memory Bound Vector Operations

Paolo Ienne, Gabriel Falcao Paiva Fernandes, João Miguel Morgado Pereira Vieira

To reduce the average memory access time, most current processors make use of a multilevel cache subsystem. However, despite the proven benefits of such cache structures in the resulting throughput, conventional operations such as copy, simple maps and red ...

IEEE2018