Publications associées à Timing closure

LUT-Based Optimization For ASIC Design Flow

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa

In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LUT-netw ...

2021

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

Francesco Regazzoni, Andrea Felice Caforio, Subhadeep Banik, Muhammed Fatih Balli

In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. In the past there have been numerous papers that have looked at circuit level implementation of block ciphers ...

IEEE2021

System, device and method for quantum correlation measurement with single photon avalanche diode arrays

Edoardo Charbon, Claudio Bruschini, Ivan Michel Antolovic

A system for photon correlation of an illuminated object and/or a light source, including a light source for illuminating the object or to correlate, an optical system having an object-facing side configured to face the object or the light source and a pro ...

2020

Trading off Energy versus Accuracy in Modern Computing Systems

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Edoardo Charbon, Francesco Regazzoni

This work proposes the first fine-grained configurable cell array specifically tailored for the implementation of cryptographic algorithms that can be configured using widely adopted hardware description languages. Our solution can be added as a small, cry ...

IEEE2018

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Edoardo Charbon, Scott Anthony Lindner, Martin Wolf

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier i ...

2017

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Mathias Soeken, Anupam Chattopadhyay

Latest quantum technologies promise realization of extremely large circuits, whereas, reversible logic synthesis, the key automation step for quantum computing suffers from scalability bottleneck. Sealability can be achieved with Decision Diagram (DD)-base ...

ACM/IEEE2016

Boolean logic optimization in majority-inverter graphs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent alge ...

2016

Majority-Inverter Graph: A New Paradigm for Logic Optimization

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we propose a paradigm shift in representing and optimizing logic by using only majority (MAJ) and inversion (INV) functions as basic operations. We represent logic functions by Majority-Inverter Graph (MIG): a directed acyclic graph c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

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Timing closure

LUT-Based Optimization For ASIC Design Flow

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

System, device and method for quantum correlation measurement with single photon avalanche diode arrays

Trading off Energy versus Accuracy in Modern Computing Systems

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Boolean logic optimization in majority-inverter graphs

Majority-Inverter Graph: A New Paradigm for Logic Optimization

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Graph Chatbot

Chattez avec Graph Search

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Majority-Inverter Graph: A New Paradigm for Logic Optimization

LUT-Based Optimization For ASIC Design Flow

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

System, device and method for quantum correlation measurement with single photon avalanche diode arrays

Trading off Energy versus Accuracy in Modern Computing Systems

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Boolean logic optimization in majority-inverter graphs