SynopsysSynopsys est une entreprise américaine spécialisée dans le développement de logiciels destinés principalement aux fabricants de semi-conducteurs, d'ordinateurs et d'équipements électroniques. On peut les regrouper en différentes catégories : La simulation avec VCS L’émulation avec Zebu-Server La synthèse logique et l'insertion de test avec Design Compiler L'analyse de timing avec PrimeTime La génération de séquences de test scan avec TetraMAX La synthèse physique et le placement routage avec la suite Astro L'analyse statique de code source avec Coverity Prevent.
Comparison of EDA softwareThis page is a comparison of electronic design automation (EDA) software which is used today to design the near totality of electronic devices. Modern electronic devices are too complex to be designed without the help of a computer. Electronic devices may consist of integrated circuits (ICs), printed circuit boards (PCBs), field-programmable gate arrays (FPGAs) or a combination of them. Integrated circuits may consist of a combination of digital and analog circuits.
Silicon compilerA silicon compiler is a electronic design automation software tool that is used for high-level synthesis of integrated circuits. Such tool takes a user's specification of a IC design as input and automatically generates an integrated circuit (IC) design files as output for further fabrication by the seminconductor fabrication plant or manually from discrete components. The process is sometimes referred to as hardware compilation. The silicon compiler may use vendor's Process Design Kit for the production.
Simulateur logiqueLogic simulation is the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation can be performed at varying degrees of physical abstraction, such as at the transistor level, gate level, register-transfer level (RTL), electronic system-level (ESL), or behavioral level. Logic simulation may be used as part of the verification process in designing hardware. Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design.
Tool Command Language(abréviation : Tcl) est un langage de script initialement conçu en 1988 par John Ousterhout et son équipe à l'université de Californie à Berkeley. Il s'inspire principalement des langages C, Lisp, sh et awk. Ce langage à typage dynamique est multiplateforme, extensible, facile à apprendre et repose sur 12 règles syntaxiques. Tcl s'interface très aisément avec le langage C, ce qui lui permet de servir par exemple d'interprète embarqué dans des applications.
AccelleraAccellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufacturing. It is less constrained than the Institute of Electrical and Electronics Engineers (IEEE) and is therefore the starting place for many standards. Once mature and adopted by the broader community, the standards are usually transferred to the IEEE.
