Standard cell | EPFL Graph Search

In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard-cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices. Construction of a standard cell A standard cell is a group of transistor and interconnect structures that provides a boo

Adaptive Body Biasing in Strong Body Factor Technologies

Thomas Christoph Müller

With the advent of intelligent sensor nodes in everyday life, low power aspects of system design become more and more important. Adaptive body biasing is a promising methodology to achieve dynamic adaptation of the tradeoff between performance and energy by shifting the threshold voltage of transistors in a digital design. This approach, in combination with a low supply voltage, provides a strong knob to the designer to rapidly shift the circuits operating point from deep sub threshold operation for slow and low leakage retention, to fast, higher performance operation to for short, but demanding tasks. This thesis concentrates on such designs using the deeply depleted channel technology in which body control is particularly effective. The first part of this thesis is dedicated to strategies and tools supporting the digital design process of circuits using adaptive body biasing. A methodology to compare a standard cell library characterised in different operating points, defined by supply voltage, process corner, temperature, and bias points is presented first. Next, we present a methodology to exhaustively and rapidly map out the supply-voltage/bias-voltage design space using a heavily pruned cell library. We extract speed and power of a simple example design across the entire design space and show a methodology to scale the characteristics of the small reference up to a more complex design. In a case study this modelling approach achieves an error of less than 1% on the total power relative to an actual characterisation of the full library at the same design point. The second part of the thesis analyses three chips implementing different biasing schemes in USJC 55nm DDC. The first two were designed by CSEM with components and measurements contributed from this thesis while the third one was entirely designed for this thesis. The first chip utilises a biasing scheme based on the first order approximation that the circuit speed is proportional to the on-current which can be driven by PMOS and NMOS transistors. This is implemented using an analog control loop, setting both PMOS and NMOS on-currents equal to a reference current provided by current DAC. The SoC characterisation is presented with the objective of identifying suitable operating modes and bias points, including a reliability and retention analysis of the SRAM. A series of ring oscillators constructed from the most common standard cells has also been integrated and provides measurement support for the first part of the thesis. The second chip extends the Calanda biasing scheme with a secondary regulation loop that is based on an FLL, designed in this thesis, in combination with a configurable standard cell based ring oscillator. The user can directly program a target frequency and the biasing system regulates the current DAC accordingly. We show that this approach effectively overcomes the drawbacks of the current based approach resulting in an effective regulation. Finally the third chip presents a novel biasing scheme that was designed in this thesis and is tailored toward simplicity. It utilises two constant voltages for the PMOS bias to switch between retention and operation. A charge pump controlled by a standard cell compatible distributed on current balance sensor regulates the NMOS bias such that the on-currents of PMOS and NMOS match. We show that this simple approach, in conjunction with a well chosen operating point, can be efficient across corners.

EPFL2021

A new interconnect-centric design methodology for high-speed standard cells with crosstalk immunity

Ilhan Hatirnaz

One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the same process generation. This situation is mainly exacurbated by the lack of suitable design tools and methodologies that can properly take into account the real implications and limitations of very deep submicron (VDSM) and nanometer scale technologies. The limitations are largely related to the signal integrity problems, caused by shrinking feature sizes with each new process. Crosstalk, for example, is one of the major issues because it results in unpredictable circuit behavior. This may cause significant timing variations, if not functional failures. Similarly, device and interconnect parasitics become harder to calculate, especially with irregular layout geometries. Accurate and early prediction of such problems, on the other hand, is virtually not possible with the existing tools. Meanwhile, the custom circuits become less affordable because of the skyrocketing design and manufacturing costs. At this point, the gate-array-like structures are becoming an increasingly popular alternative for rapid, low-cost realization of Integrated Circuits (ICs), filling the gap between Field-Programmable Gate-Arrays (FPGAs) and full-custom ASICs. In this work, the main goal is to provide an interconnect-centric design methodology, for which the underlying thinking is prevention over treatment of all these issues. Therefore, a "recipe" is described on how to early characterize these problems and address them even before they appear later during the implementation process. A simple generic RLCK interconnect model is developed and used to systematically characterize the interconnects of various geometries for delay, power and crosstalk noise. The superior performance of the differential interconnects in comparison to mainstream single-ended lines has lead to addressing the insufficient support of the Electronic Design Automation (EDA) tools for differential signaling. A complete RTL-to-GDSII differential design flow is developed that utilizes the advanced design tools through netlist conversion scripts. The advantages of differential signaling are merged with gate-level regularity in a mask-programmable cell fabric suitable for structured ASIC applications, where the basic building block is a via-programmable universal logic gate in MOS current-mode logic (MCML). The MCML design style offers good speed performance and addresses the noise immunity and crosstalk problems thanks to its differential operation. The unit cell can realize all functions up to 3-input and some of the 4-input and 5-input functions. The implementation of benchmark circuits with the proposed fabric have shown that the associated cost is acceptable when compared to the alternatives (standard-cell ASIC and FPGA). Finally, a novel design methodology is proposed which is based on correct-by-construction approach and is claimed to be a better candidate for future designs in nanometer technologies. The methodology is flexible in the sense that it makes it easier to model and to integrate emerging problems through its simulation based design exploration approach, which, in the scope of this thesis, has been focused on interconnect-related issues only. With case studies it is shown that the number of design flow iterations can be dramatically reduced or even removed by better guiding the physical implementation tools. The results dictate the EDA tools a number of advanced features to offer and/or the designers to more strongly utilize some of the existing tool capabilities, in order to manage the ever increasing design complexity.

EPFL2006

MOS current-mode logic standard cells for high-speed low-noise applications

Stéphane Badel

With the continuous shrinking of devices dimensions in microelectronic circuits, it is becoming extremely desirable to integrate analog circuitry together with complex digital logic blocks. The noise generated by the digital parts in a mixed-signal integrated circuit is inevitably transmitted to the analog parts, through the power supply networks and through the common silicon substrate. Therefore, in the past years a lot of attention has been drawn to alternative digital logic circuit styles that are more friendly than classical CMOS in a mixed-signal environment. MOS Current-Mode Logic (MCML) is a differential logic circuit style that provides high-speed operation together with low generation of supply noise, and is thus a natural candidate for implementing digital blocks in mixed-signal circuits. In this work, MOS Current-Mode Logic circuits are studied, with a focus on the implementation of standard-cell based digital circuits. To this aim, a design methodology is proposed to build efficient MCML standard-cell libraries, and a complete top-down design flow allowing the construction of complex digital circuits with differential standard-cells is proposed. The results of implementing a digital encoder block for analog-to-digital applications are presented.

EPFL2008