Publications associées à Logic optimization

Analysis of Coupled Scalar Systems by Displacement Convexity

Rüdiger Urbanke, Nicolas Macris, Rafah El-Khatib

Potential functionals have been introduced recently as an important tool for the analysis of coupled scalar systems (e.g. density evolution equations). In this contribution we investigate interesting properties of this potential. Using the tool of displace ...

Ieee2014

BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Logic Decomposition

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Despite the impressive advance of logic synthesis during the past decades, a general methodology capable of efficiently synthesizing both control and datapath logic is still missing. Indeed, while synthe- sis techniques for random control logic (AND/OR-int ...

2013

MIXSyn: An Efficient Logic Synthesis Methodology for Mixed XOR-AND/OR Dominated Circuits

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We present a new logic synthesis methodology, called MIXSyn, that produces area-efficient results for mixed XOR-AND/OR dominated logic functions. MIXSyn is a two step synthesis process. The first step is a hybrid logic optimization that enables selective a ...

2013

SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Catherine Lucie Jéromine Gasnier

Devices with controllable-polarity, such as Double-Gate Vertically-Stacked Nanowire FETs, have shown promising interests in recent years to implement XOR-based logic functions in an unprecedented compact way. Such a compactness is obtained at the cost of a ...

2013

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We present a novel class of decision diagrams, called Biconditional Binary Decision Diagrams (BBDDs), that enable efficient logic synthesis for XOR-rich functions. BBDDs are binary decision diagrams where the Shannon’s expansion is replaced by the bicondit ...

2013

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba, Michele De Marchi

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

Identifying and modeling the integrated design process of net Zero Energy buildings

Marilyne Andersen, Shady Galal Mohamed Attia, Emmanuel Walter

High Performance Buildings (HPB), including Net Zero Energy Buildings (NZEBs) and nearly Zero Energy Buildings (nZEB) are emerging as an important market in Europe and around the world. However, there are very few studies that aim to model the process of H ...

2013

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

2012

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Logic optimization

Analysis of Coupled Scalar Systems by Displacement Convexity

BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Logic Decomposition

MIXSyn: An Efficient Logic Synthesis Methodology for Mixed XOR-AND/OR Dominated Circuits

SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Identifying and modeling the integrated design process of net Zero Energy buildings

On Gm-boosting and cyclostationary noise mechanisms in low-voltage CMOS differential Colpitts VCOs

On Synthesis for Unbounded Bit-vector Arithmetic

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Graph Chatbot

Chattez avec Graph Search

BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Logic Decomposition

On Gm-boosting and cyclostationary noise mechanisms in low-voltage CMOS differential Colpitts VCOs

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Analysis of Coupled Scalar Systems by Displacement Convexity

MIXSyn: An Efficient Logic Synthesis Methodology for Mixed XOR-AND/OR Dominated Circuits

SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Identifying and modeling the integrated design process of net Zero Energy buildings

On Synthesis for Unbounded Bit-vector Arithmetic