Bloc d'alimentation

Résumé

Le bloc d’alimentation (power supply unit en anglais, souvent abrégé PSU), ou simplement l’alimentation ou alim, d'un PC est le matériel informatique l'alimentant. L’alimentation est chargée de convertir la tension électrique du secteur en différentes tensions continues TBT, compatibles avec les circuits électroniques de l’ordinateur. Fonctionnement en technologie L’alimentation fournit du courant électrique à l’ensemble des composants de l’ordinateur. Le bloc d’alimentation doit posséder une puissance suffisante pour alimenter les différents périphériques de ce dernier. Elle convertit la tension alternative de ou en diverses tensions continues utilisées par la carte mère et les périphériques (disque dur, lecteur CD…). Aux États-Unis et au Canada, les blocs d’alimentation reçoivent une tension à et à , tandis qu’en Europe la norme est de à une fréquence de 50 Hz ; c’est la raison pour laquelle les blocs d’alimentation possèdent la plupart du temps un commutateur pe

Source officielle

https://fr.wikipedia.org/wiki/Bloc_d'alimentation

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La carte mère est le circuit imprimé qui supporte la plupart des composants et des connecteurs nécessaires au fonctionnement d'un compatible PC. Elle est essentiellement composée de circuits imprimés

Un ordinateur de bureau ou ordinateur fixe (desktop computer en anglais) est un ordinateur personnel destiné à être utilisé sur un bureau ou tout autre endroit fixe à cause de ses dimensions, de sa m

L'ordinateur personnel (en anglais : personal computer ou PC) se confond aujourd'hui avec le micro-ordinateur ou ordinateur individuel : c'est un ordinateur destiné à l'usage d'une personne, de prix

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Conventional RF power amplifiers usually give their maximum efficiency near the maximum output power level. When the output power decreases, the efficiency drops sharply. Deep class AB or B PAs improve their efficiency by a self-adaptation of the current drawn from the power supply. However, in many cases, both deep class AB and B do not provide enough linearity like, for instance, in CDMA applications where spectral re-growth is of first concern. From class A to class B, RF PAs face the linearity-efficiency trade-off. The class A is linear but power inefficient, whereas class B is efficient but has a poor linearity. An alternative to the linearity-efficiency trade-off is to dynamically adapt the power supply voltage of a linear PA with respect to the instantaneous envelope value of the modulating signal. The linear PA is of class A or class AB and its collector or drain voltage is adapted to avoid RF output voltage to saturate such that, ideally, the linearity is not degraded. The supply voltage adaptation should be capable to follow large envelope bandwidth for CDMA application (3.8MHz for UMTS and 1.2MHz for IS-95). This thesis work treats System and modulator design aspects. System aspects covers mainly the PA bias influence on the system linearity and system simulation issues. The modulator design covers the architecture aspect to address bandwidth and efficiency requirements and the design in a CMOS 0.35µm process. The modulator is a fast high efficiency step down converter providing all necessary functions to transform the main power supply according to the low envelope detected level into a varying supply for an external PA. The typical carrier frequency is around 1900MHz with a typical minimum level of 100µW whereas the PA power consumption is in the order of a couple of hundred milliwatts.

EPFL2004

Chargement

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).

EPFL2009

Chargement

A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems

Yao Shi

We present a fully integrated energy reservoir unit using a counter flow method for peak power delivery in space-constrained sensor systems. Recent advances in circuits have enabled significant reduction in the size of wireless systems such as implantable biomedical devices. As a consequence, the batteries integrated in these systems have also shrunk, resulting in high internal resistances (~10 kQ). However, the peak current requirement of power-hungry components such as radios remains in the milliwatt range and hence cannot directly be supplied from the battery. Therefore, an energy reservoir with high output power but small size is required. We present an efficient energy reservoir that dynamically reconfigures a storage capacitor array using a so-called counter flow approach. By creating a voltage gradient on capacitor arrays and moving the capacitors along the slope of the gradient, the supply voltage can be maintained while the energy stored in the reservoir is delivered efficiently to the load. The counter flow energy reservoir delivers 65% of stored energy before recharging is needed which allows up to a 12× reduction in overall capacitor size compared with our implementation of the previous method. The design supplies up to 13.6-mW output power for 1 μs. We demonstrate the proposed concept with a pulsed radio, showing an 11.5× increase in pulse length compared with the previous method.

IEEE2017

Chargement

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

EPFL2009