Concept

Cell (processeur)

Publications associées (243)

A Fundamental Limit of Distributed Hypothesis Testing Under Memoryless Quantization

Ali H. Sayed, Emre Telatar, Mert Kayaalp, Yunus Inan

We consider a distributed binary hypothesis testing setup where multiple nodes send quantized information to a central processor, which is oblivious to the nodes’ statistics. We study the regime where the type-II error decays exponentially and the type-I e ...

2021

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

Load cell with adjustable stiffness based on a preloaded T-shaped flexure pivot

Simon Nessim Henein, Charles Baur, Loïc Benoît Tissot-Daguette, Michal Stanislaw Smreczak

In this paper, we present a new flexure-based load cell with adjustable stiffness designed for force sensors with extended force range and respective measuring resolution. This novel monolithic mechanism consists of a T-shaped flexure pivot combined with a ...

euspen2021

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow cell arrays (FCAs) provide efficient on-chip liquid cooling and electrochemical power generation capabilities in three-dimensional multi-processor systems-on-chip (3DMPSoCs). When connected to power delivery networks (PDNs) of chips, the current flowi ...

2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Mirjana Stojilovic, Philip Brisk, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...

IEEE COMPUTER SOC2020

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon, Yasir Mahmood Qureshi

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

Real-time high-resolution omnidirectional imaging platform for drone detection and tracking

Jean-Philippe Thiran, Selman Ergünay, Yusuf Leblebici, Vladan Popovic, Bilal Demir, Gökçen Nurlu

Drones have become steadily affordable, which raises privacy and security concerns as well as interest in drone detection systems. On the other hand, drone detection is a challenging task due to small dimensions of drones, difficulty of long-distance detec ...

SPRINGER HEIDELBERG2019

Single-photon avalanche diode imagers in biophotonics: review and outlook

Edoardo Charbon, Claudio Bruschini, Ivan Michel Antolovic, Harald Arjan Robert Homulle, Samuel Burri

Single-photon avalanche diode (SPAD) arrays are solid-state detectors that offer imaging capabilities at the level of individual photons, with unparalleled photon counting and time-resolved performance. This fascinating technology has progressed at a very ...

2019

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

2019

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