High Speed Packet Access

Résumé

High Speed Packet Access (HSPA), aussi appelé 3G+ dans sa dénomination commerciale, est la combinaison de deux protocoles utilisés en téléphonie mobile pour améliorer les performances obtenues avec la 3G UMTS : le High Speed Downlink Packet Access (HSDPA) et le High-Speed Uplink Packet Access (HSUPA). Débit maximum théorique Ils permettent d'atteindre des débits théoriques maximum de en descente et en montée selon la mise en service de ces deux normes par les opérateurs et la compatibilité du terminal utilisé. En France

SFR proposait fin 2010 des débits 3G+ en aval jusqu'à sur l'ensemble de son réseau mobile et dans 76 % de son réseau. Son réseau a ensuite évolué en 2012 (comme ceux de ses concurrents) vers la technologie HSPA+.
Orange proposait fin 2010 des débits 3G+ en descente jusqu'à sur l'ensemble de son réseau et expérimentait le débit dans villes françaises. En 2012, Orange annonce que 50 % de la population de France métropolitaine est couv

Source officielle

https://fr.wikipedia.org/wiki/High_Speed_Packet_Access

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Le LTE (Long Term Evolution) est une évolution des normes de téléphonie mobile GSM/EDGE, CDMA2000, TD-SCDMA et UMTS. La norme LTE, définie par le consortium 3GPP, a d'abord été considérée comme

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Bridging the gap between dataplanes and commodity operating systems

Georgios Prekas

The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and microsecond-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. In particular, dataplanes borrow design elements from network middleboxes to run tasks to completion in tight loops. In its basic form, the dataplane design leverages sweeping simplifications such as the elimination of any resource management and any task scheduling to improve throughput and lower latency. As a result, dataplanes perform best when the request rate is predictable (since there is no resource management) and the service time of each task has a low execution time and a low dispersion. On the other hand, they exhibit poor energy proportionality and workload consolidation, and suffer from head-of-line blocking. This thesis proposes the introduction of resource management to dataplanes. Current dataplanes decrease latency by constantly polling for incoming network packets. This approach trades energy usage for latency. We argue that it is possible to introduce a control plane, which manages the resources in the most optimal way in terms of power usage without affecting the performance of the dataplane. Additionally, this thesis proposes the introduction of scheduling to dataplanes. Current designs operate in a strict FIFO and run-to-completion manner. This method is effective only when the incoming request requires a minimal amount of processing in the order of a few microseconds. When the processing time of requests is (a) longer or (b) follows a distribution with higher dispersion, the transient load imbalances and head-of-line blocking deteriorate the performance of the dataplane. We claim that it is possible to introduce a scheduler to dataplanes, which routes requests to the appropriate core and effectively reduce the tail latency of the system while at the same time support a wider range of workloads.

EPFL2018

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IX: A Protected Dataplane Operating System for High Throughput and Low Latency

Edouard Bugnion, Ana Klimovic, Christos Kozyrakis, Georgios Prekas

The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and microsecond-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. We present IX, a dataplane operating system that provides high I/O performance, while maintaining the key advantage of strong protection offered by existing kernels. IX uses hardware virtualization to separate management and scheduling functions of the kernel (control plane) from network processing (dataplane). The dataplane architecture builds upon a native, zero-copy API and optimizes for both bandwidth and latency by dedicating hardware threads and networking queues to dataplane instances, processing bounded batches of packets to completion, and by eliminating coherence traffic and multi-core synchronization. We demonstrate that IX outperforms Linux and state-of-the-art, user-space network stacks significantly in both throughput and end-to-end latency. Moreover, IX improves the throughput of a widely deployed, key-value store by up to 3.6x and reduces tail latency by more than 2x.

USENIX2014

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The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and μs-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. We present ix, a dataplane operating system that provides high I/O performance and high resource efficiency while maintaining the protection and isolation benefits of existing kernels. ix uses hardware virtualization to separate management and scheduling functions of the kernel (control plane) from network processing (dataplane). The dataplane architecture builds upon a native, zero-copy API and optimizes for both bandwidth and latency by dedicating hardware threads and networking queues to dataplane instances, processing bounded batches of packets to completion, and eliminating coherence traffic and multicore synchronization. The control plane dynamically adjusts core allocations and voltage/frequency settings to meet service-level objectives. We demonstrate that ix outperforms Linux and a user-space network stack significantly in both throughput and end-to-end latency. Moreover, ix improves the throughput of a widely deployed, key-value store by up to 6.4× and reduces tail latency by more than 2× . With three varying load patterns, the control plane saves 46%--54% of processor energy, and it allows background jobs to run at 35%--47% of their standalone throughput.

Association for Computing Machinery2016

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Bridging the gap between dataplanes and commodity operating systems

Georgios Prekas

EPFL2018