Model-checking intends to verify whether a property is satisfied by a model, or not. Model-checking of high-level models, e.g. SysML models, usually first requires a model transformation to a low level formal specification. The present papers proposes a ne ...
We present an exact approach to synthesize temporal-logic formulas in linear temporal logic (LTL) from a set of given positive and negative example traces. Our approach uses topology structures, in particular partial DAGs, to partition the search space int ...
This paper presents a semantic foundation of temporal conceptual models used to design temporal information systems. We consider a modelling language able to express both timestamping and evolution constraints. We conduct a deeper investigation of evolutio ...
New architectures of telecommunications networks like the Intelligent Network (IN) proposal allow an ever easier way to introduce new services into a network. However, this facility and the short delays that can be achieved between the first informal speci ...
Vertically-stacked Silicon NanoWire FETs (SiN- WFETs) with gate-all-around control are the natural and most advanced extension of FinFETs. At advanced technology nodes, due to Schottky contacts at channel interfaces, devices show an ambipolar behavior, i.e ...
