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Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

Gain-Cell Embedded DRAMs: Modeling and Design Space

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Gain-Cell Embedded DRAMs: Modeling and Design Space

Gyrokinetic simulations on many- and multi-core architectures with the global electromagnetic Particle-In-Cell Code ORB5

Gyrokinetic simulations on many- and multi-core architectures with the global electromagnetic Particle-In-Cell Code ORB5

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

Gain-Cell Embedded DRAMs: Modeling and Design Space

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Gain-Cell Embedded DRAMs: Modeling and Design Space