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Timing Violation Induced Faults in Multi-Tenant FPGAs

Design Guidelines for High-Performance SCM Hierarchies

Optimized Memory Access For Dynamically Scheduled High Level Synthesis

The telomeric DNA damage response: Insights into telomere compaction and identification of novel damage signaling factors

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

An Accelerator for High Efficient Vision Processing

The Mondrian Data Engine

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

The telomeric DNA damage response: Insights into telomere compaction and identification of novel damage signaling factors

Optimized Memory Access For Dynamically Scheduled High Level Synthesis

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

Design Guidelines for High-Performance SCM Hierarchies

The Mondrian Data Engine

Timing Violation Induced Faults in Multi-Tenant FPGAs

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

An Accelerator for High Efficient Vision Processing