Tableau associatif

En informatique, un tableau associatif (aussi appelé dictionnaire ou table d'association) est un type de données associant à un ensemble de clefs, un ensemble correspondant de valeurs. Chaque clef est associée à une seule valeur (au plus) : un tableau associatif correspond donc à une application de domaine fini en mathématiques. Du point de vue du programmeur, le tableau associatif peut être vu comme une généralisation du tableau : alors que le tableau traditionnel associe des entiers consécutifs à des valeurs, le tableau associatif associe des clefs d'un type arbitraire à des valeurs d'un autre type. Les opérations usuellement fournies par un tableau associatif sont :

ajout : association d'une nouvelle valeur à une nouvelle clef ;
modification : association d'une nouvelle valeur à une ancienne clef ;
suppression : suppression d'une clef ;
recherche : détermination de la valeur associée à une clef, si elle existe.

Les tableaux associatifs sont utilisés couramment en informat

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Séances de cours associées (28)

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Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Mikhail Asiatici, Paolo Ienne

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which typical caches provides little benefit because of very frequent misses. Non-blocking caches are widely used on CPUs to reduce the negative impact of misses and thus increase performance of applications with low cache hit rate; however, they rely on associative lookup for handling multiple outstanding misses, which limits their scalability, especially on FPGAs. This results in frequent stalls whenever the application has a very low hit rate. In this paper, we show that by handling thousands of outstanding misses without stalling we can achieve a massive increase of memory-level parallelism, which can significantly speed up irregular memory-bound latency-insensitive applications. By storing miss information in cuckoo hash tables in block RAM instead of associative memory, we show how a non-blocking cache can be modified to support up to three orders of magnitude more misses. The resulting miss-optimized architecture provides new Pareto-optimal and even Pareto-dominant design points in the area-delay space for twelve large sparse matrix-vector multiplication benchmarks, providing up to 25% speedup with 24x area reduction or to 2x speedup with similar area compared to traditional hit-optimized architectures.

ASSOC COMPUTING MACHINERY2019

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Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Mikhail Asiatici, Paolo Ienne

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24x area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

ASSOC COMPUTING MACHINERY2022

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Twisting structures and strongly homotopy morphisms

Kathryn Hess Bellwald

In an application of the notion of twisting structures introduced by Hess and Lack, we define twisted composition products of symmetric sequences of chain complexes that are degreewise projective and finitely generated. Let Q be a cooperad and let BP be the bar construction on the operad P. To each morphism of cooperads g from Q to BP is associated a P-co-ring, K(g), which generalizes the two-sided Koszul and bar constructions. When the co-unit from K(g) to P is a quasi-isomorphism, we show that the Kleisli category for K(g) is isomorphic to the category of P-algebras and of their morphisms up to strong homotopy, and we give the classifying morphisms for both strict and homotopy P-algebras. Parametrized morphisms of (co)associative chain (co)algebras up to strong homotopy are also introduced and studied, and a general existence theorem is proved. In the appendix, we study the particular case of the two-sided Koszul resolution of the associative operad.

2010

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